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64Gbit NAND tailored on 20nm class process

Posted: 18 Oct 2010     Print Version  Bookmark and Share

Keywords:NAND  flash memory  20nm process 

Samsung Electronics Co. Ltd has started production of 64Gbit NAND tailored on 20nm process with three bits per memory cell that suits USB flash drives and secure digital memory cards.

Samsung says it had introduced a "20nm-class" 32Gbit multi-level cell NAND flash memory in April this year, leading to speculation that the company was trying to make a 27nm process appear on a par with 26-, 25- and 24nm process claims rival companies. In August, Toshiba Corp. announced that it had begun mass production of 64Gbit NAND flash memories using a 24nm CMOS manufacturing process technology and thereby taken the lead in geometry and NAND flash density.

Others say that as process geometry goes below 30nm, measurements of gate length and metal pitch become variable; even line edge roughness can make a difference.

Samsung and others are starting to refer to the 3X generation as a node with critical dimensions somewhere between 30- and 40nm. Similarly the 2X-node or 20nm class refers to a process with critical dimensions between 20nm and 30nm.

Samsung's 20nm-class, 64Gbit NAND flash memory has a 60 per cent higher productivity level than Samsung's existing 30nm-class, 32Gbit NAND. The device also offers improved performance by applying the Toggle DDR 1.0 specification, a step up from the Single Data Rate data transmission of the 30nm-class NAND chips.

The availability 8GB of storage in a single chip will trigger the acceptance of Toggle DDR-based high-performance flash in a variety of applications include smart phones, Samsung said.

- Peter Clarke
EE Times





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