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Tilera unveils third gen multi-core processors

Posted: 30 Sep 2010     Print Version  Bookmark and Share

Keywords:multi-core processors  wireless infrastructure  digital video transcoding 

Fabless chip vendor Tilera Corp. unveils its third generation of multi-core processors which target an array of applications including cloud computing, digital video transcoding, wireless infrastructure and advanced networking. The highlight of this generation is a SoC that features 100 64bit cores

Presenting at the Linley Tech Processor Conference, Bob Doud, director of marketing at Tilera, said the company's Tile-Gx product line would offer performance increases of two to eight fold compared to the company's current TilePro family. Doud said 16- and 36-core Tile-Gx devices would be sampling by the end of this year and that 64- and 100-core iterations of the family would begin sampling in mid-2011.

The 100-core Tile-Gx100, first announced by Tilera last October, will feature clock speeds of between 1Ghz and 1.5GHz, 32 megabytes of total cache and 546 gigabit per second peak memory. As with previous Tilera products, the Tile-Gx devices will feature a mesh or "tile" 64bit RISC processor architecture, which connects the cores through Tilera's proprietary iMesh on-chip network. Doud said the devices would support a broad range of high-speed interfaces, including XAUI, Double XAUi, SGMII, Interlaken, PCI Express and StreamIO. The devices will also feature several co-processing engines, including Tilera's proprietary Multicore iMesh Coprocessing Accelerator (MiCA).

Tilera's tile architecture

Graphical depiction of Tilera's tile architecture, which the company says is power efficient and highly scalable. Source: Tilera Corp

Doud emphasized the advantage of Tilera's tile architecture, which emphasizes modular design and power efficiency and is, according to Doud, highly scalable to a large number of cores. As chip vendors move forward with expanding the number of cores available on an SoC, the industry needs architectures that allow that scale so that it is not necessary to "reinvent the architecture for each new advance in core count," Doud said.

"There isn't really a limit to what you can do with this tile architecture," Doud said. "We think this is the way of the future."

Asked about similarities between its architecture and the mesh architecture developed years ago by researchers at the University of Texas-Austin, Doud said,

"What makes Tilera stand apart from research that has been done at UT Austin and Intel is that we are in commercial production with two generations of chips."

Later, Doud added, "We are seeing a lot of other companies embracing mesh. We encourage that. We think that mesh is the way to go in the future. We just have a little bit of a lead."

Earlier at the conference, Linley Gwennap, principal analyst at the Linley Group, said revenue from dual-core and multi-core processors will account for only about 25 per cent of networking and communications chip revenue in 2010. Noting that the long development cycle means that design wins take three to five years to translate into revenue, Gwennap said revenue from dual-core networking and communications chips is projected to surpass single-core revenue in 2013.

-Dylan McGrath
EE Times





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