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Sandy Bridge features dual-threaded x86 cores

Posted: 17 Sep 2010     Print Version  Bookmark and Share

Keywords:CPU  sandy bridge architecture  x86 cores  graphics core  interconnect 

Intel Corp. revealed that the company's Sandy Bridge family of heterogeneous 32nm computer processors, coming in versions with two or four dual-threaded x86 cores and one graphics core on a shared ring interconnect, are expected to be released before April 2011.

Sandy Bridge links last-level cache blocks and cores on a ring(Click on image to enlarge.)

The first chips are designed for notebooks, desktops and single-socket servers. Versions featuring more cores targeting multi-socket servers will follow later in 2011 or early in 2012.

The Sandy Bridge CPUs will compete directly with those from Advanced Micro Devices, including the Ontario, a 40nm CPU using two of AMD's new Bobcat cores and a Microsoft DirectX11-class graphics core. Ontario is sampling now, and AMD has similar desktop and server chips in the works for 2H 2011.

Engineers at the 2010 Intel Developer Forum said their new graphics block will not support the DirectX 11 API, thus AMD will have an edge in graphics. However, Intel's chips are offering enhancements in its processor that will help it compete in other areas.

"There are no exclusive DX11 games out today, and DX11 is around the corner for Intel based products," said Tom Piazza, an Intel fellow who led the graphics core design.

Neither company has provided information on performance, data rates and cache sizes. It is expected that both company's desktop chips are likely to be held to two DDR3 external memory channels, a limit set by PC makers, said Opher Kahn, a senior principal engineer on Sandy Bridge.

Other low level details of Sandy Bridge that were revealed include the use of a ring interconnect that could scale to link as many as 20 cores on a die, this was according to Kahn.

Intel re-used much of the electrical design of previous rings on Intel's previous Westmere and Larrabee processors. However, they re-worked much of the higher-layer coherency protocols for Sandy Bridge.

The interconnect is made up of at least four rings, a 32B data link and separate rings for requests, acknowledgements and snooping. The rings are overlaid on the design of the so-called last-level cache.

The cache is broken up into separate units, one per x86 core. Each cache block is responsible for its own coherency in a distributed structure that does not require a central arbiter.

The ring delivers about 96Gbit/s per connection at a 3GHz data rate, as much as four times the on-chip bandwidth available to Intel's previous processor cores. It takes one clock cycle for data to progress one step on the ring. Traversing the full ring could take 26 to 31 clocks, Kahn estimated.

Intel is far from unique in its use of rings. The latest eight-core network processors from NetLogic Microsystems also use a ring interconnect.

- Rick Merritt
EE Times





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