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Pin-limited test solution claims low test time

Posted: 16 Sep 2010     Print Version  Bookmark and Share

Keywords:pin-limited test  test compression  manufacturing test 

Synopsys Inc. revealed that Silicon Image Inc., a provider of semiconductors and IP for secure distribution, presentation and storage of high-definition content, has adopted Synopsys' DFTMAX compression, an integral part of the Galaxy implementation platform, to address test requirements for mixed-signal designs with tight packaging constraints claiming significantly lower manufacturing test cost and time.

Silicon Image's mixed-signal multimedia design testing requirements included a tight form factor and a limited number of package pins. Using the pin-limited test capability in DFTMAX, Synopsys stated that Silicon Image designers were able to implement test compression for the mixed-signal chip in just two days, substantially reducing test time, data and cost while achieving high test coverage.

"Because of the tight form factor of our package, only three scan input-output pairs were available for testing our design," said Narasimha Nookala, senior director of IC engineering at Silicon Image. "DFTMAX compression for pin-limited test reduced test time and data by more than 95 per cent while maintaining high defect coverage, making it a key component in the rigorous testing process we employ to deliver high quality products."

The demand for more functionality, smaller area and lower cost is leading to more stringent IC packaging constraints that limit the number of pins that can be allocated for test. In addition, to manage the complexity of large systems-on-chip, designers are deploying core-based methodologies that restrict access of embedded test compression logic to only a few chip-level pins. Multi-site testing, a technique that targets multiple die simultaneously to reduce test time, is also stimulating the demand for pin-limited test because each die has access to fewer tester channels.

Synopsys recently extended DFTMAX compression to enable predictable high compression for designs and methodologies that mandate as few as one pair of test data pins. Built into the Galaxy implementation platform to eliminate time-consuming iterations between synthesis, scan insertion and physical implementation, Synopsys' DFTMAX compression and TetraMAX automatic test pattern generator (ATPG) offer designers a comprehensive solution for meeting their most challenging quality and cost goals for test.

"Increased focus on packaging size and cost is driving the need to utilise fewer pins for manufacturing test," said Bijan Kiani, VP of product marketing at Synopsys. "Silicon Image and other Synopsys customers are now benefiting from the superior quality of results attainable using DFTMAX compression to lower the cost of pin-limited testing."





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