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UHS-II PHY IP provides high-speed memory interface

Posted: 07 Sep 2010     Print Version  Bookmark and Share

Keywords:IP core  memory cards  non-volatile memory interface 

Arasan Chip Systems Inc. reveals that it has developed a low-power, compact, highly integrated ultra high speed (UHS)-II PHY IP core designed using mixed signal design and verification methodology. UHS-II is a next-generation memory interface being finalized by the SD association. Arasan is an executive member of the SD association, and has been working with its customers who are productizing the interface.

The quick growth of portable media players, DSCs, smart phones, netbooks and gaming consoles has led to the proliferation of non-volatile memory cards to store and distribute HD content. The SD 3.0 specification defines cards with a maximum memory capacity of 2TB and interface bandwidth that scales up to 104MBit/s in UHS-I.

Anticipating requirements for next-generation gaming and multimedia applications, the SD Association has defined the UHS-II standard that achieves peak interface speeds of 3.12Gbit/s in full duplex mode and 1.56Gbit/s in half duplex mode.

The UHS-II PHY IP core is available in leading process nodes at multiple foundries. This core can be used in SD host, device as well as other SDIO configurations. It has been architected to enable easy customer integration and custom porting to any fab process in a timely manner, to speed up customer time to market.

Arasan offers a total IP solution for the PHY IP core consisting of behavioural model, timing model, GDS II database, LEF model and a LVS netlist. Complementing the core is a complete set of industry leading SD/SDIO IP controller cores available in multiple configurations.





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