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Bobcat, Bulldozer put in an appearance

Posted: 01 Sep 2010     Print Version  Bookmark and Share

Keywords:x86  core  Bobcat  Bulldozer 

The second integer pipeline requires only 12.5 per cent more die area. Performance for the dual-core approach varies with workloads but "we often see an 80 per cent boost" compared to 20 per cent or less for the simultaneous multi-threading technique Intel uses, said Chuck Moore, an AMD corporate fellow and chief technology officer of technology development.

Essentially, AMD is betting that by packing the most critical hardware elements of two cores in a single core design it can outperform Intel which double-tasks one pipeline with its so-called Hyperthreading approach.

However, Intel has yet to reveal the architecture of its 2011 Sandybridge chips which may use a third-generation approach to symmetric multi-threading or follow AMD's lead to include more hardware resources. Intel's Sandybridge chips will be its second generation of 32nm processors and the first to integrate graphics and x86 cores on a single die.

 <b>AMD's Bulldozer marries two integer and one shared floating point units</b>

AMD's Bulldozer marries two integer and one shared floating point units.

Each integer block in Bulldozer has a 16KB L1 data cache. They share a 64KB instruction cache. Processors using the cores will implement a wide variety of secondary and tertiary caches, some using no L3 cache at all.

The floating point unit will implement new vector instructions similar to those expected in Intel's next-generation Sandybridge chips which also ship in 2011. The Bulldozer floating point unit includes two 128-bit multiply-accumulate units, the first x86 to have such dedicated hardware, Moore said.

AMD faces big execution risks with Bulldozer given the amount and complexity of new technology in the core, said analyst Brookwood.


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