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Engineers discuss 3D chip standard

Posted: 19 Jul 2010     Print Version  Bookmark and Share

Keywords:3D chip standard  Through-Silicon Vias  Semicon West 

Participants of a Semicon West 2010 workshop took the first crack at outlining standards for 3D silicon chips to address design, yield and cost problems.

Linking stacks of chips with tiny silicon vias promises smaller devices that need less power to deliver greater performance for a variety of applications. But engineers said a wide range of standards are needed to design and make such chips.

Researchers said no show-stopping technical hurdles stand in the way of creating the so-called through-silicon vias (TSVs). But there are multiple approaches to designing and making such chips, yields are still low and costs are high— problems standards can address.

"Hopefully we can kick off key working groups to start developing some standards," said Urmi Ray a senior staff engineer at Qualcomm who organised the workshop and helped develop prototype 3D chips for cell phones. "We want the technology to be adopted quickly so we can get to revenue," she said.

"We think there is a strong need for some form of standardisation to accelerate the adoption of the technology and lead to cost reduction," said Arifur Rahman, a principal engineer at Xilinx who outlined in a keynote talk some of the areas to address.

Rahman said engineers need a full chip-to-chip interface standard that could be similar to the Jedec standard for a wide I/O DRAM interface. The stacks may use thousands of the links, some less than 25 microns long carrying data at Gbit/s rates.

Designers also need interoperable EDA tools that take into account stacks using chips made in different process technologies, he said.

In manufacturing, 3D chips require standards in silicon wafers, chip materials and fab processes. A metrology engineer at Sematech described two dozen standards that need to be redefined to modify fab tools or processes for 3D ICs.

"If you are going to do this stuff I strongly recommend you take your tools out for a test drive, but you can use standard 300mm tools," said Andy Rudack, a Sematech researcher in 3D interconnects at the Albany, New York research lab.

Sematech has run bare 300mm wafers though a set of fab process tools including some packaging tools which have never been used in a fab clean room. Next year it expects to run fully processed 130nm or 65nm wafers through a 3D process.


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