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FPGA platform integrates TCP offload engine

Posted: 08 Jun 2010     Print Version  Bookmark and Share

Keywords:FPGA  development platform  PCIe 

Intilop Corp.'s FPGA-based platform integrates TCP offload engine (TOE) SoC IP and PCIe to increase the ability to customise the product for various applications.

The Xilinx V5 and V6 FPGA-based development platforms provide system solutions for TCP offload engine SoC IP. The platform integrates some features of TCP/IP protocol in hardware which provide differentiated levels of TCP/IP performance improvement.

Different TOE features can be incorporated for different type of network traffic.

Intilop believes this is the first TOE development platform available that is customisable for many different types of applications. The benefits include increasing the raw throughput or response time of an e-mail or Web server, reducing the number of ports in a switch.

All of TCP-connection related tasks, TCP-payload transfer tasks, TCP-disconnection, TCP-session management overhead, which traditionally are performed by TCP/IP software, are accomplished by the hardware engines in TOE resulting in an order magnitude performance improvement.

It can also be customised to meet other requirements such as miscellaneous protocol processing and monitoring at multi-Giga-bit line rate, number of simultaneous connections, and TCP/IP performance tuning based upon type of network/traffic and application usage, scalable packet FIFO size, scalable size of session management table, session parameters, scalable size of direct store Packet memories, integrated DDRn/SSRAM controllers (optional), choice of PHY interface—GMII or serial and more.

- Colin Holland
Programmable Logic DesignLine





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