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Stratix FPGAs integrate 28Gbps transceivers

Posted: 21 Apr 2010     Print Version  Bookmark and Share

Keywords:FPGA  DSP  ASIC  Ethernet 

Altera said its 28nm Stratix V family would include four variants: Stratix V GT, featuring integrated 28Gbps transceivers targeting 100G systems and beyond; Stratix V GX, featuring 600Mbps to 12.5-Gbps transceivers; Stratix V GS, optimised for high-performance digital signal processing (DSP) applications with 600Mbps to 12.5Gbps transceivers; and Stratix V E, suited for ASIC prototyping, emulation or high-performance computing applications.

Stratix V GX and Stratix V GS pack up to 66 high-performance, low-power transceivers operating up to 12.5Gbps.The will also feature tweaks to Altera's adaptive logic module (ALM) architecture, adding up to 800,000 additional registers in the largest device to maximise logic efficiency, Altera said. The ALM architecture is suited for heavily pipelined and register-rich designs, the company said.

Variable-precision DSP block
With Stratix V, Altera also plans to introduce what it refers to as the industry's first variable-precision DSP block, offering high efficiency and performance across multiple-precision DSP data paths. According to Schirrmeister, the DSP block includes a small area of memory storage, enabling it greater speed and efficiency.

"This DSP block allows the customer to dial in the efficiency they need," Schirrmeister said.

Stratix V FPGAs will also include a seven-by-72bit 1,600Mbps DDR3 memory interface and LVDS channels capable of operating at 1.6Gbps on ubiquitous I/Os, Altera said.

The Stratix V would also incorporate hard IP for functions including PCIe Gen3, Gen2, Gen1, 40G/100G Ethernet, CPRI/OBSAI, Interlaken, Serial RapidIO 2.0 and 10GbE 10GBASE-R. Memory interfaces with hardened read/write paths include DDR3, RLDRAM II and QDR II+, the company said.

In addition, the Stratix V FPGAs would support and meet compliance for a number of 3G, 6G and 10G protocols and electrical standards such as 10G/40G/100G, Interlaken and PCI Express Gen 3, Gen2, Gen 1. The devices also provide direct interoperability to 10G backplanes and optical modules, the company said. The 28Gbps transceivers within the Stratix V devices are designed to meet the CEI-28G specification, and consume only 200mW per channel.

Altera expects to begin shipping samples of Stratix V FPGAs in Q1 10. The devices will be supported with Quartus II software version 10.0 in beginning later Q2 of this year.

- Dylan McGrath
EE Times


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