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How MCUs can extend ADC resolution/accuracy

Posted: 26 Mar 2010     Print Version  Bookmark and Share

Keywords:integrated ADC  ADC resolution accuracy  ADC in MCU 

This technique requires an ADC with high sampling rate (to increase the resolution without sacrificing the input-signal bandwidth), and an integrated buffer for storing samples. The buffer also helps to reduce the microprocessor overhead. ADCs embedded in MCUs are well suited for this technique, if their integral nonlinearity (INL) and differential nonlinearity (DNL) are in line with the resolution desired.

The oversampling approach can be applied to just about any MCU with an embedded ADC, so to see exactly how it's done, we use a 16-bit RISC-based MCU (Maxim's MAXQ2010) to demonstrate the averaging and oversampling control. The MAXQ2010 incorporates a 12-bit, 312-ksps ADC with 1 LSB of INL and DNL. This MCU (and similar MCUs from other vendors) often include several architectural features that help simplify the oversampling scheme:
� Ability to interrupt on each conversion, each sequence, or on every 12 or 16 samples.
� Capable of taking a single sample, a sequence of samples, or a continuous sequence of samples.
� Inclusion of a 16-word sample buffer.

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Figure 4: Multiple registers within this MCU support the internal ADC by storing the configuration bits and buffering the captured samples.

Similarly, most MCUs include registers associated with the ADC that store control parameters for the ADC sequencer and other functions (Figure 4). In the MAXQ2010, the following CPU registers control the ADC sequencer:
� ADCN (ADC Control Register): Bits in this register control the ADC's sample acquisition extension, power management override, single/continuous sequence conversion, interrupt intervals, and clock division.
� ADST (ADC Status Register): Bits in this register include the register-index selection bits ADCFG (ADC configuration register) and ADBUF (ADC sample buffer register), the conversion start bit, and other status bits for the ADC.
� ADADDR (ADC Conversion Sequence Address Register): Bits in this register define the first and last ADCFG registers used in a conversion sequence, as well as the first ADBUF register written in a conversion sequence.
� ADDATA (ADC Data Register): Bits in this register serve as read/write access pointers to registers ADCFG[7:0] and ADBUF[15:0].
� ADCFG[7:0] (ADC Sequence-Configuration Registers): These eight conversion-configuration registers provide settings for each individual conversion in an ADC conversion sequence. Configuration registers for the start and end of the sequence are given by the SEQSTART and SEQEND bit fields in the ADADDR register.
� ADBUF[15:0] (ADC Sample Buffer Registers): A read-only register that contains the ADC conversion result.

Assuming we want to achieve 14 bits of resolution on ADC channel 0, we can use the programming sequence in Listing 1. The ADC control register (ADCN) is configured for continuous conversion and for generating an interrupt signal every 16 ADC samples. The bit configuration is shown in Figure 5a.

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Listing 1: Here�s a programming sequence to achieve 14bits of resolution on ADC channel 0.

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Figure 5: The ADC control register (ADCN) is configured for continuous conversion and for generating an interrupt signal every 16 ADC samples.

ADDAIE = 1 (An interrupt will be triggered)

ADCONT = 1 (Continuous conversion sequence mode)

IREFEN = 1 (Internal reference is used)

ADINT[1:0] = 11 (Interrupt every 16 ADC samples)


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