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TMS320DM36x VICP algorithms and codecs integration

Posted: 25 Jan 2010     Print Version  Bookmark and Share

Keywords:codec integration  VICP algorithms  TMS320DM36x VICP 

TMS320DM36x devices have two accelerator sub-systems: HD video imaging co-processor (HDVICP) and VICP. The HDVICP engine is suitable for running H.264 encode/decode, while the VICP engine is suitable for running various imaging algorithms, such as video noise filter (VNF) and de-interlacing (DEI), and codecs such as MPEG4 and MJPEG. In the full system, it is desirable to run the HDVICP and VICP engines concurrently to achieve the wider use case with best performance in the system. This application note intends to help users to design algorithms and H.264 codec to co-exist and work in parallel. It talks about various codec and system level considerations.

View the PDF document for more information.





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