Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Embedded
 
 
Embedded  

Achieving timing closure in basic (PMA direct) functional mode

Posted: 05 Jan 2010     Print Version  Bookmark and Share

Keywords:timing closure  Stratix Altera  FPGA 

Transceiver channels configured in Basic (PMA Direct) functional mode only use the physical medium attachment (PMA) blocks of the transceiver channels. The physical coding sub-layer (PCS) blocks of all channels are bypassed.

The interface between the transceivers and the FPGA core introduces significant delay on the clocks that are forwarded from the transceivers to the user logic in the FPGA core. A phase-compensation FIFO buffer in the transceiver PCS block compensates for the phase difference (due to delays) between the transceiver clocks used internally and the ones routed to and from the FPGA core. When transceivers are used in Basic (PMA Direct) functional mode, the phase-compensation FIFO buffer is bypassed because the entire PCS block is bypassed. The result is that the timing requirement is not easily met for the transmit side of the transceiver beyond certain interface frequencies.

This application note describes two methods to achieve timing closure for designs that use transceivers in Basic (PMA Direct) mode at higher data rates for Altera's Stratix IV GX or Stratix IV GT FPGAs.

View the PDF document for more information.





Comment on "Achieving timing closure in basic (P..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top