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VLSI conference tackles 2010 design challenges

Posted: 28 Dec 2009     Print Version  Bookmark and Share

Keywords:International Conference on VLSI Design  VLSI Design Conference  3D architecture  MEMS 

Mehendale: The conference serves as a great forum for India's design engineers to listen to the experts on the specific domains they are working on, understand future trends.

Started 23 years ago, the International Conference on VLSI Design organised by the VLSI Society of India (VSI) has become one of the leading events in India focusing on EDA, IC design and, more recently, embedded systems design. Scheduled Jan. 3-7, 2010 in Bangalore, the event presents three days of tutorials, industry presentations, panel discussions, design contests and vendor exhibits.

The 2009 conference attracted over 500 visitors with the organisers aiming for 700 in 2010. A first this year is virtual participation with the three conference tracks streamed live to engineers' desktops.

EE Times-India's Vivek Nanda asked Dr. Mahesh Mehendale, director, Centre of Excellence for Digital Video, Texas Instruments India, to talk about the conference. Mehendale is one of the two general chairs of the conference and the only TI Fellow in Asia.

What key technologies will the conference introduce to India's design engineers?
Mehendale: The conference offers a five-day technical programme, with the goal of having worldwide experts present on near-term, mid-term and long-term challenges. This serves as a great forum for India's design engineers to listen to the experts on the specific domains they are working on, understand future trends. It also serves as a forum for researchers both in academia and in industry to share their latest research output with a strong technical community. The first two days of the conference feature full-day tutorials. The next three days include, in addition to the regular paper sessions, keynote speeches and invited talks on hot topics of interest. The conference will also feature Jan. 5-6 an "industry forum" with presentations on hot topics from the technologists of leading semiconductor and EDA companies. More than 20 companies will showcase their latest technologies, tools, chips and system solutions on the exhibition floor.

What key challenges to the electronics design community does the conference plan to address?
Mehendale: The conference plans to address multiple challenges (both near term as well as longer term) that the VLSI design community faces, including the following.

As CMOS scaling continues from 40nm to 28nm to 22nm, each node poses new design challenges related to increased variability, leakage power management, reliability, etc. The shrinking geometries also pose challenges for the analogue components integrated in most of the SoCs. These are covered by Dr. Greg Taylor in his keynote address on Jan. 7. We also have an embedded [design] tutorial by Dr. Ruchir Puri on Jan. 6 addressing design and CAD challenges at 22nm and beyond. The keynote address by Dr. Yervant Zorian on Jan. 7 discusses another important aspect of managing IP risks as we navigate through the new process nodes.

As CMOS scaling is getting increasingly complex and expensive, researchers have started exploring technologies which will continue to drive the increasing levels of integration. These include three-dimensional integration, associated with it innovative packaging technologies, new materials beyond silicon and new structures, such as carbon nanotubes. This aspect is covered by Professor Dimitri Antoniadis in his keynote address titled "Nanoelectronics challenges for the 21st century" on Jan. 5. We also have a session on 3D ICs, which will include an embedded tutorial titled "Novel Architecture Design with Three-dimensional (3D) Integration Technology" by Dr. Y. Xie on Jan. 7.

As the industry is gradually getting out of the recession, Asia (primarily China and India) has clearly emerged as the market that will drive the growth. These markets have unique requirements that the future electronic product development has to address. These markets are cost sensitive. The low cost (affordable) solutions for these markets will require high-tech innovations, such as massive integration to drive down the cost of a mobile phone. The keynote address by Dr. Hermann Eul on Jan. 5 covers this challenge and discusses opportunities for differentiation in a highly competitive wireless handset market.

In terms of applications, security, energy and healthcare have emerged as important market segments. The applications not only drive the requirements of low power and reliability aggressively, they also require system-level integration of heterogeneous technologies—including sensors, microfluidic biochips and MEMS. The keynote address by Dr. Larry Hornbeck on Jan. 5 discusses digital micro-mirror device (DMD) technology. We have an embedded tutorial by Professor Kaushik Roy on Jan. 5 on "Designing low-cost energy-efficient complex systems using heterogeneous components" and another by Professor Krishnendu Chakrabarty on Jan. 7 on digital microfluidic biochips.


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