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Intel moves tera-scale efforts mainstream

Posted: 04 Dec 2009     Print Version  Bookmark and Share

Keywords:Intel multicore effort  x86  processor 

Chip giant Intel Corp. has re-positioned its "tera-scale" processor R&D efforts, moving towards a more mainstream, x86-based multicore design instead of a proprietary technology.

At a press event, Intel demonstrated an experimental, 48-core processor—or "single-chip cloud computer"—based on a 45nm process using high-k and metal-gate technology. In the future, Intel's so-called "single-chip cloud computer" processor could enable PCs to use "vision" to interact with people.

More importantly, the device is based on a "two-core in a tile" scheme and Intel Architecture (IA)—or x86-based—technology. Intel will release a few devices to limited partners for use in software development, said Justin Rattner, head of Intel Labs and Intel's chief technology officer.

Among those partners include ETH Zurich, Microsoft, University of California at Berkeley and the University of Illinois.

The new device is somewhat different than Intel's previous "tera-scale" R&D MPU programme. In 2007, Intel demonstrated its Teraflop Research Chip—code-named Polaris. The 80-core chip was not a x86-based device; instead, it was a proprietary technology that was positioned more as a "mainframe-on-a-chip."

Now, Intel is taking a more mainstream approach to this multicore effort by going the x86-based route. Intel has nicknamed this test chip a "single-chip cloud computer" because it resembles the organisation of datacenters used to create a "cloud" of computing. Cloud datacenters are comprised of tens to thousands of computers connected by a physically cabled network, distributing large tasks and massive datasets in parallel.

The long-term research goal for Intel's new device is to add scaling features that spur new software applications and human-machine interfaces. Intel plans to build 100 or more experimental chips for use by dozens of industrial and academic research collaborators. The goal is to develop new software applications and programming models for future multicore processors.

This prototype device itself contains of 48 programmable processing cores. It also includes a high-speed, on-chip network for sharing information along with new power management techniques. The on-chip network technology was also present on Polaris, Rattner said.

On-chip networking allows all 48 cores to operate energy efficiently at as little as 25 watts, or at 125 watts when running at maximum performance. This is about as much as today's Intel processors and just two standard household light bulbs.

"With a chip like this, you could imagine a cloud datacenter of the future which will be an order of magnitude more energy efficient than what exists today, saving significant resources on space and power costs," said Rattner. "Over time, I expect these advanced concepts to find their way into mainstream devices, just as advanced automotive technology such as electronic engine control, air bags and anti-lock braking eventually found their way into all cars."

- Mark LaPedus
EE Times





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