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Global conference series makes a pit stop at India

Posted: 17 Nov 2009     Print Version  Bookmark and Share

Keywords:Cadence conference series  CDNLive! coverage  India semiconductor industry 

Aiming to gather design engineers and industry experts to help solve design challenges, Cadence's CDNLive! is a global series of technical conferences for the company's technology and service users. This year, the conference is making a pit stop at India on Nov. 18-19, 2009. EE Times-India caught up with Rahul Arya, marketing and technical sales director at Cadence Design Systems (I) Pvt. Ltd, to discuss India's domestic semiconductor industry and to find out what Indian engineers should expect at the conference.

EE Times-India: What technical challenges face Indian engineers, and what major trends does CDNLive! aim to address?
Rahul Arya: Indian engineers are currently dealing with the challenges in analogue mixed-signal (AMS) design, power optimisation, verification IPs, system-in-package (SiP) and design for manufacturing (DFM). And CDNLive! aims to explore these challenges and create solutions for these markets.

The design process for most of today's electronics is getting complex as consumers want multiple functionalities in gadgets—such as mobile phones, netbooks, smart books, music players etc.—with ever decreasing form factors. These designs need to seamlessly integrate analogue and digital hardware and software. To achieve this kind of complex design, no chip design process can be purely analogue or digital in nature, thus calling for AMS design. A platform approach is very important in AMS design, as all the tools have to work together. Moreover, AMS design needs strong foundry support for manufacturability—EDA companies need to ensure that their tools provide a smooth and efficient path from design through manufacturing.

Power optimisation is another significant challenge across industries—from mobile consumer devices to high-end computing servers. This is because customers and businesses are pushing for greener electronics. As designs migrate to sub-90nm process nodes, power management becomes critical across the entire design and manufacturing chain. This calls for energy efficiency at the system and application levels for wired and wireless products. There is a need for applications that allow applications and systems developers to evaluate how their programs use power both individually and as part of a dynamic, multi-application model of the end system. Existing design techniques need to be upgraded to automate power-lowering design techniques.

Ensuring design predictability is another challenge. For semiconductor design companies, the productivity of design teams is a key business imperative as they have to deliver value while keeping operating costs in check. Time-to-market pressures and short product lifecycles also imply that the product has to be out in the market within a very tight window for it to be cost-effective and profitable. As a result, chip designers need the entire design process to be more predictable and thereby more efficient. Designers would like predictability that allows them to plan for IP selection, and run analysis around power, performance and budget for the costs involved. As a result, verification IPs are critical to chip design.

Most of these complex designs are developed at advanced process nodes—such as 65nm and 45nm—and pose challenges, especially during manufacturing. Timing delays, gate leakage, pattern fidelity, proximity and thermal effects, and random defects are all amplified at advanced nodes. These challenges particularly occur while designing SiP, since any defective chip in the package will result in a non-functional packaged IC, even if all other modules in that same package are functional. These technical and business complexities call for some innovative circuit design, as design companies and in turn their customers can't afford silicon re-spins. Hence, DFM is essential to restrict and solve the problems at the design level, and well before they reach the manufacturing stage. Today, EDA-enabled accurate modelling solutions for DFM technologies are emerging to solve these problems.

Tell us about the sessions that address these challenges.
CDNLive! is a global series of technical conferences that brings together electronics designers and engineers that use Cadence technologies and services.

At CDNLive!, customers share their designs, the challenges they faced, solutions discovered, specs exceeded and new techniques developed. The attendees learn from peers who have been there.

At CDNLive! India 2009, we have over 45 sessions, including five roadmap presentations that cover the breadth and depth of design.

The Verification Track sessions cover the overall challenge of conceptualisation to implementation, IP reuse, hardware/software validation, power-aware design verification and other challenges of verifying highly complex designs.

In the Digital IC Track, attendees will hear about effectively dealing with power issues, DFM challenges at low process nodes, and achieving predictability in timing and SI closure of their designs.

In the Custom IC Track, sessions discuss floorplanning for mixed-signal design using Open Access, custom layout, AMS verification, power grid sign off, and fast and accurate Spice simulation.

In the Front End Design Track, sessions focus on engineering change orders (ECOs) and their impact on the design process, low power challenges in the front end flow, advanced formal verification challenges, and architectural exploration.

In the PCB and IC Packaging Track, we look at packaging trends and challenges, SIP solutions, library development and conversion, and SI issues.

How many Cadence partner companies are participating in CDNLive?
We have over 20 customers presenting multiple papers at the event, including ARM, CDAC, Cisco Systems, Freescale, IBM, Kamal Electronix, LSI Research, Motorola Penang, NXP, Rambus, Sandisk, Sonic Chips, ST Microelectronics, Tessolve, Texas Instruments, Wipro and Xilinx.

Our worldwide sponsors for CDNLive! are ARM, Common Platform and TSMC. Our media sponsor is EE Times-India.

Looking back at 2009, what impact has downturn had on the Indian market?
Due to the overall downturn in the economy and cautious customer spending on electronics, many companies in the semiconductor ecosystem have experienced slow or negative growth this year. Our customers' customers are delaying purchase decisions, thus impacting the overall semiconductor and electronics industry. On the positive side, some prominent companies have "called the bottom." In addition, we understand there has been an up tick in orders at the foundries.

In spite of the global slowdown, things are looking relatively better for the Indian domestic semiconductor market. According to the ISA-Frost & Sullivan report update 2008-10, the total revenues of the Indian semiconductor market are poised to grow from Rs.28,820.40 crore ($5.9 billion) in 2008 to Rs.37,075.73 crore ($7.59 billion) in 2010 at a CAGR of 13.4 per cent, marking a growing market despite a decline in the growth rate. The India market itself is a growth driver and companies—multinational and local—are actively exploring the opportunities.

- EE Times-India





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