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Low-power ADCs offer design options

Posted: 29 Oct 2009     Print Version  Bookmark and Share

Keywords:data converter  ADC  signal processing 

Low-power ADCs

Analog Devices Inc. announces 26 new ADCs suited for effective high-performance, power-efficient communications, portable device, instrumentation and health care applications. ADI is a leader in data-conversion technology for signal processing applications.

The AD9269 is the claimed to be the first 16bit 80MSps low-power, dual ADC with quadrature-error correction (QEC). The AD9265 is the touted to be first single-channel, 16bit low-power ADC spanning 80-125MSps. And the AD9266 is the smallest, single-channel 16bit low-power ADC spanning 20- to 80MSps.

These ADCs give designers a flexible, future-proof platform to differentiate their systems without changing the core design by migrating either resolution or bandwidth support by means of space efficient pin compatible families. Their energy efficiency provides significant power consumption improvement without impacting system-level performance.

Aside from these three, ADI has introduced 23 single-channel low-power ADCs, bringing the number of low power data converters ADI has brought to market in the last 180 days to 44. The power consumption savings across these ADCs is as high as 87 per cent compared to equivalent competitive offerings operating comparable ADC functions.

The dual-channel AD9269 16bit low-power ADC consumes 93mW per channel, which is 6.5x lower than competing devices. It is a monolithic, dual-channel 16bit, 20-/40-/65-/8MSps ADC, featuring a high-performance sample-and-hold circuit and on-chip voltage reference. It's also the first 16bit ADC family to include a QEC and DC offset digital processing block. These blocks dynamically minimise the errors produced in an in-phase/quadrature (I/Q) complex signal receiver system. By using the QEC block, system designers can relax component matching requirements by reducing gain and phase errors due to component mismatches. The net result can also enable a more robust receiver design. In addition, the DC-offset algorithm minimises offsets commonly found in DC-coupled applications. The product uses multi-stage differential pipeline architecture with output error correction logic to provide 16bit accuracy at 80MSps data rates and guarantees no missing codes over the full operating temperature range. The ADC operates from a 1.8V supply and contains several features designed to maximise flexibility and minimise system cost, such as programmable clock and data alignment and programmable digital-test-pattern generation. Samples are available now with production quantities available in January 2010.

Meanwhile, the single-channel AD9265 low-power, 16bit ADC was designed to support communications applications requiring low BOM costs, small size and flexibility. Consuming only 370mW, this represents a 51 per cent savings compared to competitive low-power solutions. The ADC core features a multi-stage, differential pipelined architecture with integrated output error correction logic. The AD9265 features a wide bandwidth differential sample-and-hold analogue input amplifier supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabiliser provides means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The ADC output data are either parallel 1.8V CMOS or 1.8V LVDS (DDR). Flexible power-down options allow significant power savings, when desired. Programming for setup and control are accomplished using a 3bit SPI-compatible serial interface. Production quantities are available now.

The single-channel AD9266 16bit, low-power ADC is available in a small 5mm x 5mm package, and the pin-out supports resolutions from 10- to 16bits. The low-power, multi-stage ADC core is based on a proprietary, high-performance, sample-and-hold circuit and on-chip voltage reference. The product uses a differential-pipeline architecture with output-error-correction logic to provide 16bit accuracy at 80MSps data rates and guarantees no missing codes over the full operating temperature range. The ADC contains several features designed to maximise flexibility and minimise system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the SPI. A differential clock input controls all internal conversion cycles. An optional DCS compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data are presented in offset binary, Grey code, or twos complement formats at DDR low-voltage CMOS levels. A data output clock is provided to ensure proper latch timing with receiving logic. Samples are available now with production quantities available in January 2010.





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