Global Sources
EE Times-India
 
EE Times-India > EDA/IP
 
 
EDA/IP  

Designing networks with FPGAs gets easy

Posted: 24 Sep 2009     Print Version  Bookmark and Share

Keywords:FPGA  software  design support  telecommunications 

Easing design
Xilinx Targeted Design Platforms enable designers to quickly start SoC development, evaluate Xilinx technology, and rapidly adapt targeted reference designs to the specific feature requirements of their systems. As part of the Xilinx Base Targeted Design Platform, the Spartan-6 FPGA SP605 and Virtex-6 FPGA ML605 Evaluation Kits provide everything needed to evaluate the serial capabilities in Virtex-6 LXT and Spartan-6 LXT FPGA devices.

The company will roll out its Connectivity Targeted Design Platform later this year with complete targeted reference designs for implementing XAUI to PCIe and Gigabit Ethernet to PCIe bridging solutions, including Direct Memory Access cores to achieve optimised bandwidth. As part of this platform, Virtex-6 HXT devices provide the silicon foundation for the Xilinx deployment of ultra high-speed connectivity development kits and market-specific development kits targeting broadcast video and wired connectivity, packet processing, and traffic management applications.

Virtex-6 HXT FPGAs extend Xilinx serial technology leadership with the new high-speed serial GTH transceiver. This latest innovation in transceiver technology is part of Xilinx's holistic approach to serial system design that goes beyond silicon to address system-level connectivity requirements. Xilinx considers use models, ease-of-use, signal and data integrity, IP, and board designs to enable faster deployment of customer solutions, starting from the architecture phase through product rollout.

With five generations of serial design experience and the most advanced 40- and 45nm process technologies, Xilinx is able to provide designers with the right transceiver for the application at hand.

Serial system development targeting Virtex-6 HXT FPGAs can begin immediately with ISE Design Suite 11.3. The development environment reflects the way logic designers and signal integrity experts work, while providing access to the flexibility and advanced capabilities required to implement both well-established protocols as well as advanced cutting-edge protocols as they emerge. Intellectual property cores from Xilinx Alliance members Sarance and Avalon are available for Virtex-6 HXT devices to accelerate design of 100G solutions.

Virtex-6 HXT device samples will be available starting in December. The ISE Design Suite 11.3 is available now with full design support for all Virtex-6 and Spartan-6 FPGAs and is list priced starting at Rs.1.46 lakh ($2,995) for the Logic Edition. Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx website.

For application notes and technical articles on FPGAs, visit Embedded Design India.


 First Page Previous Page 1 • 2



Comment on "Designing networks with FPGAs gets e..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top