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Execs tackle ASIC, FPGA design challenges

Posted: 22 Sep 2009     Print Version  Bookmark and Share

Keywords:SoC design  FPGA  ASIC  design flow 

The ASIC versus FPGA debate took an interesting turn, as executives from two design tool firms offered duelling keynote address on the virtues of and challenges facing FPGA-based and ASICs-based SoCs designs.

The keynotes, which kicked off the EE Times System-on-chip Virtual Conference, were delivered by Rajeev Madhavan, chairman and CEO of EDA vendor Magma Design Automation Inc., and Gerry Gaffney, president of the U.S. subsidiary of Australian design tool provider Altium Ltd.

Gaffney argued that architecture beyond the ASIC is needed to help designers meet goals for 21st Century products in a forthcoming era that he predicted would be dominated by connected intelligence ecosystems, where electronic hardware is less important than a product's ecosystem and the end-user experience.

"Consumers no longer care what goes on under the hood from a hardware perspective within a device," Gaffney said. He added that the value of Apple's iPod, for example, is not really in the hardware, but in the supporting tools and end-user experience.

A competitor could replicate the iPod hardware, but cannot easily replicate the end-user experience, including Apple's iTunes software interface, Gaffney said.

Future designers will need to be more generalists, less hardware focused, Gaffney said. While hardware, programmable hardware and software designs have traditionally been separate activities and still are within many companies, 21st Century design challenges demand a holistic approach, Gaffney said.

A new design approach is required, allowing designers to innovate around powerful and flexible FPGA-based SoC platforms, Gaffney said. He described FPGAs as a key enabling architecture.

"It's the reprogramability of FPGAs which will allow them to play a much greater starring role at the heart of tomorrow's products," Gaffney said.

Magma CEO Madhavan, on the other hand, argued that ASICs-based SoC designs are not money pits if properly managed even though costs can quickly spiral out of control, potentially derailing product development plans and leaving manufacturers and semiconductor supply partners vulnerable to lower priced options from competitors.

Running away from the cost challenge is not a viable option even when deploying ASICs-based designs versus FPGA alternatives, according to Madhavan, who stated that careful planning and intense focus on cost-control combined with the use of next-generation methodologies can help designers and equipment makers can successfully deploy and squeeze out the best return on investment from their SoC designs.

In his presentation titled "Deriving ROI from Next-Generation SoCs," Madhavan said developers must contend early with the potential cost of their designs and take steps early on to maximise returns by focusing on high-volume applications and "adopting efficient design methodologies

The modern SoC design process is plagued with numerous challenges, including complex mixed-signal design flows, time-consuming technology migration issues related to digital components, the design of which often get more complicated at smaller geometries, and still inflexible licensing models at design automation services companies.

To offset these problems, Madhavan suggested designers adopt a three-pronged strategy of first increasing the amount of differentiated mixed-signal and analogue content and second, using cost-effective SoC design flow, including "digital-fast," a process he describes as "high capacity, multi-processed flow that delivers the same turnaround time for next-generation designs as today's."

Lastly, manufacturers must "consider flexible, cost-effective project based licensing for managing large scale ASICs-based SoCs." Of course, they would need to find partners willing to help them achieve these goals even as rivals look for ways to deliver the same competitive products to market using FPGA-based SoC designs.

- Dylan McGrath and Bolaji Ojo
EE Times





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