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IBM Power7 fires up multi-core server bout

Posted: 27 Aug 2009     Print Version  Bookmark and Share

Keywords:processor  multi-core  IBM server  DDR3 

IBM Corp. might just walk away from the Hot Chips conference with bragging rights to having the most muscular microprocessor with its Power7. The eight-core, 45nm chip is expected to set new watermarks in parallelism and cache that could translate into leading-edge performance for servers using it.

Addressing the broader market for x86-based systems, Advanced Micro Devices will describe its 12-core Magny-Cours, its first to use a multi-chip module. Intel Corp. will detail its Nehalem EX, a souped-up version of the Xeon 5500 that debuted earlier this year.

Sun Microsystems, still waiting for approval of its merger with Oracle Corp., will present the latest version of its Sparc-based Niagara processor at the annual processor confab hosted by Stanford University.

When the dust settles, IBM likely will stand above the competition. The Power7 is expected to support as much or more cache, threads and memory bandwidth as any of the competition.

"I am sure Power7 will be the fastest processor around, probably faster than Intel's Nehalem in some benchmarks," said Nathan Brookwood, principal of market watcher Insight64.

Among its several advances, Power7 uses a mix of SRAM and IBM's embedded DRAM technology to pack on to the same die as the processor as much or more cache as any of its competitors. That's a big shift from the past three Power generations that used cache on separate die in a multi-chip module.

The shift from the two-core Power6 to the four-, six- and eight-core Power7 drove the need for more memory, a change that took years of effort both in IBM's silicon-on-insulator process technology and in memory architecture, said Bill Starke, an IBM Power architect who has worked on four generations of Power chips.

"We knew when we hit this level of multi-core design, we would have to make the shift," Starke said. "We've been talking about this for several processor generations," he said.

The eDRAM cache of more than 32MB, improved off-chip signalling techniques "and a few more ingredients," helped IBM get beyond the 300GBps memory bandwidth of the Power6. In addition, Power7 is said to pack as many as eight DDR3 memory channels.

"IBM will have far greater memory bandwidth than anyone else, and that matters because with multi-core design the issues is getting data in fast enough to feed the beast and the Power7 beast will be well fed," said Brookwood.

Early reports suggested Power7 had at least 16MB eDRAM. But the paper revealed IBM packed a whopping 32 MB eDRAM as L3 cache on the 567mm² chip.

The Power7 is expected to scale back on the blistering 5GHz data rate of the Power6 but ratchet up the support of multi-threading from two to as many as four threads per core, the watermark previously held only by Sun's Niagara processors.

In addition, Starke confirmed reports that IBM has embedded hardware into the CPU to ease the job of building large clusters. The feature will be used in the Blue Waters supercomputer based on Power7 that IBM is building under a U.S. government contract.

IBM is said to already have systems running in its labs using up to 32 Power7 chips. The company said it will start shipping the processors in 2010.


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