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Multicore chip operates up to 400 MIPS

Posted: 26 Jun 2009     Print Version  Bookmark and Share

Keywords:multi-core  processor  DSP 

XS1-L series

XMOS Ltd has launched the XS1-L series, its second-generation event-driven processors at only Rs.244.93 ($5) per core.

The chips provide embedded software developers with an energy-efficient, scalable, multi-core solution which enables them to build complete systems combining interface, DSP and control functions entirely in software.

Each XS1-L XCore contains a 32bit processor and operates up to 400MIPS. XCore power consumption is below 500µW in sleep mode and 20mW in standby with active power adding under 450µW/MHz. The event-driven architecture, together with XMOS' programming tools enables XCores to switch automatically between standby and active saving up to 90 per cent of energy in low duty-cycle applications—no special programming is needed.

XS1-L devices are supported by tools available free of charge from the XMOS Website. A new development kit, the XC-5, based on the XS1-L1 is also available. Because it is based on an entirely software-based design flow that uses C and the XMOS originated XC programming language, existing reference designs and design examples can be targeted at the new XS1-L family of devices.

According to James Foster, CEO of XMOS, "It is widely recognised that developers are dissatisfied with the high NREs and 6 month turn-around associated with the ASICs they are currently using. Implementing complete systems with FPGAs is just not cost-effective. Developers are crying out for a programmable solution at the right price point. XMOS event-driven processors meet this market need, providing rapid programmability in C together with tools that are easy to use."

The XS1-L1 device is currently available in a 10mm x 10mm LQFP64 package (samples available now) and a 14mm x 14mm TQFP128 package (samples available in July) both priced under Rs.244.93 ($5) for 10k unit quantities.





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