Global Sources
EE Times-India
 
EE Times-India > EDA/IP
 
 
EDA/IP  

Complex SoCs power intent verification

Posted: 15 May 2009     Print Version  Bookmark and Share

Keywords:mobile phones  complex SoCs  verification 

Today we all know why has power become the dominant constraint and a key factor for most of the applications like mobile phones, processing communications and consumer electronics. All these applications use complex SoCs which consists of different power domains, voltage domains, latches with tie low/high, isolations with tie low/high, voltage regulators and LDOs.

While we understand the driving factors and the reasons behind it, we have also come up with many verification techniques to address the continuously aggressive power reduction requirements of most ASIC and SoC designs. Some of the techniques are as follows; multi-supply multi voltage, power gating with or without state retention, dynamic voltage and frequency scaling etc. Though we have these techniques, these introduce risk to the product development schedule and impact all aspects of ASIC and SoC development which includes design, implementation, and verification.

This paper describes the basic elements of low power verification and discusses how a technology enables power-aware verification at the register transfer level (RTL). It also tackles different ways to debug the power-aware (PA) issues.

View the PDF document for more information.





Comment on "Complex SoCs power intent verificati..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top