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Highly integrated power mgt chip cuts costs

Posted: 29 Apr 2009     Print Version  Bookmark and Share

Keywords:watchdog timer  voltage supervision  reset generator 

ProcessorPM

Lattice Semiconductor has added a new member to its Power Manager II family, the ProcessorPM device, a programmable, single chip solution for the reset generation, watchdog timer and voltage supervision functions found in virtually every microprocessor or DSP design.

While priced competitively with off-the-shelf three-supply supervisor ICs, the ProcessorPM device integrates the functions of reset generator ICs with variable pulse stretch timing, watchdog timer ICs running up to two minutes, and six-supply supervisor ICs.

"The ProcessorPM device reduces our customers' costs by integrating functionality typically implemented using individual reset, supervisor and watchdog ICs," said Chris Fanning, Corporate Vice President and General Manager of Low Density and Mixed Signal Solutions. "The ProcessorPM device also provides our customers with greater design flexibility by incorporating Lattice's in-system programmability."

The ProcessorPM device provides six programmable threshold comparators (accuracy -0.7 %) with individual glitch filters to monitor up to six supply rails without using external resistors and capacitors. The comparator outputs are connected to a 16 macrocell, ruggedised on-chip PLD (programmable logic device) that generates the reset and brownout signals by using simple logic equations. Four timers can be individually programmed from 32 microseconds to 2 seconds and used for implementing watchdog timers or for reset pulse stretching. Two digital inputs can be used for manual reset inputs or for monitoring other digital inputs such as Power Down or Disable Processor signals.

All device settings are stored using on-chip non-volatile EEPROM that is programmed via a JTAG interface. Design modifications after the board is assembled, such as changing thresholds or altering timer values, can be achieved easily by modifying the design in PAC-Designer software and then downloading it into the design through JTAG. There is no need to change any resistors or capacitors.

ProcessorPM devices are preprogrammed with an initial configuration to integrate a programmable six-supply reset generator (configured through pin strapping) and a programmable watchdog timer (configured through pin strapping). This configuration can be used as is across a large number of designs. The original configuration software source code is also provided to enable integration of additional functions for further board cost reduction.

ProcessorPM designs can be implemented using the intuitive, user-friendly GUI provided in version 5.1 of the PAC-Designer software tool suite, which can be downloaded for free from the Lattice website, www.latticesemi.com/pac-designer.

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