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Sign-off flow shortens design cycle

Posted: 23 Apr 2009     Print Version  Bookmark and Share

Keywords:sign-off flow  RF design kit  EDA tools  silicon foundry 

Seeking to accelerate the product development process, Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) is rolling out a one-two punch in the arena: It has unveiled a mixed-signal/RF design kit as well as a foundry-specific integrated sign-off flow.

The mixed-signal/RF reference design kit (MS/RF RDK) initially targets 65nm process technology and aims to accelerate analogue, mixed-signal, and RF designs and RF SoC verification and integration. The MS/RF RDK is the result of multi-year collaboration between TSMC and Cadence Design Systems.

TSMC's bigger announcement, on the other hand, appears to be the so-called Integrated Sign-Off Flow, which is a turnkey EDA flow. The flow consists of specific and pre-qualified EDA and IP tools from multiple vendors, which are selected by the foundry giant. Customers must still buy the EDA tools from the third-party vendors. But because the flow has been qualified and tuned for TSMC's fabs, chip makers can bring a product to the market more rapidly by following the pre-defined and strict guidelines in the process.

The initial flow from TSMC is available for 65-nm designs. The new flow shortens the design cycle and improves tape-out quality, said Tom Quan, deputy director of design services marketing at TSMC. ''It's an executable flow,'' Quan said. ''We know there are a lot of people struggling with their own flows. We can help them.''

For years, the silicon foundry giant and its rivals have offered a design reference flow, which consists of various third-party EDA, DFM, IP and other tools. The flow provides a suggested guideline or path to enable a particular design.

In this model, chip makers must continue to evaluate and buy a complex raft of EDA, DFM and IP tools. This reference flow model works, but chip designs continue to get more complex and expensive.

To help customers, TSMC is taking another approach. Its Integrated Sign-Off Flow is a complete RTL-to-GDSII chip implementation flow. It consists of the exact and process-specific items, including pre-qualified libraries, IP and selected EDA tools.

There are some advantages in going this route. This is especially true for chip makers with lack of resources in their CAD departments. In its new flow, TSMC selects the EDA tools, as opposed to the chip maker itself. This in turn saves time and money. ''It takes an enormous amount of time to evaluate the tools,'' Quan said.

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