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Cadence enhances low-power solution

Posted: 18 Mar 2009     Print Version  Bookmark and Share

Keywords:on-chip power management  logic design technologies  power management components 

Cadence Design Systems Inc. announced that it has enhanced the Cadence Low-Power Solution to include support for new on-chip power management schemes enabled by the recently ratified Si2 Common Power Format (CPF) Version 1.1.

The enhanced solution spans the Cadence Encounter digital implementation and logic design technologies, and the Incisive functional verification and system design and verification technologies. The upgraded solution enables designers to more accurately model, analyse and debug power management components targeted for integration into large SoC designs. It includes macro modelling, seamless multi-language support for IP integration and automated support of metric-driven verification methodologies such as those in the new Cadence Incisive Enterprise Simulation Environment.

The power macro-modelling capability enables more accurate characterisation and analysis of power consumption within complex SoC IP. Additionally, the Cadence Low-Power Solution is completely generalised to enable a multitude of popular programming approaches to IP block integration, and delivers automated low-power design capabilities that extend well beyond implementation. The enhancements enable the IP block or SoC to operate as designed and within the power parameters required by the end application. One proponent of the enhanced CPF-enabled solution is Virage Logic. The company is consistently an early provider of advanced technology solutions, and over the years has broadened the power management capabilities of its SiWare Memory and SiWare Logic product lines. By using these products with the Cadence Low-Power Solution, SoC designers can more accurately analyse the benefits of the power management schemes in the context of their full designs.

Through the metric-driven Cadence Incisive Enterprise Simulation suite, the Cadence Low-Power Solution now enables automated assertion generation and automated low-power coverage for low-power intent verification; voltage-aware simulation and voltage tracking; full multi-language support for low-power verification; and powerful new debug and visualisation mechanisms.

Cadence Low-Power solution enables Fujitsu Microelectronics tape-out of 65nm WiMAX design.

- Paul Buckley
Power Management DesignLine Europe

Get Technical Papers and Application Notes on Power Design India!





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