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Unifying hardware, software verification

Posted: 05 Mar 2009     Print Version  Bookmark and Share

Keywords:functional verification  hardware description language  HDL 

When it comes to functional verification, traditionally the major bottleneck in the design process, software-based approaches, such as hardware description language (HDL) simulation, continue to lose ground. HDL simulation speeds aren't keeping pace with device complexity because many new devices—3G cell phones, internet routers and image processors, for example—require massive verification sequences that would take many years to simulate on even the fastest PC. These sequences are often a result of the need to run long, contiguous, serial protocol streams or complex embedded software to fully verify a new system on chip (SoC) or system design.

Increasingly, embedded software is overtaking the hardware content of SoC devices. The net result is a causality dilemma: which comes first—the "final" hardware or the "final" software?

In recent years, a new breed of tools, collectively called virtual prototyping platforms based on a high-level of design abstraction, have been introduced in an attempt to start software validation well ahead of silicon availability.

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