Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > T&M
 
 
T&M  

Design, validate high-speed buses

Posted: 18 Feb 2009     Print Version  Bookmark and Share

Keywords:buses  DDR  crosstalk 

This application note by Agilent is intended for digital design engineers working on high-speed buses. It covers tools and measurement techniques for validating general high-speed buses and specifically covers DDR.

The obvious technology trend today is higher clock speeds. However, the many related changes have an equal or greater impact on designs. Faster clock speeds require smaller voltage swings and shorter setup and hold times. Suddenly, data-valid windows are orders of magnitude smaller. The decreasing size of the data-valid window means that jitter-induced noise, crosstalk, and intersymbol interference further reduce itssise, creating errors. Because the noise margins are so small, noise and timing budgets can no longer tolerate phenomena that were previously ignored. Low voltage differential signalling, double-pumped clocks, and point-to-point designs can also create new challenges. Other improvements have resulted in yet more design challenges. Clock speeds are now reaching frequencies formerly used only by RF and microwave engineers.

View the PDF document for more information.





Comment on "Design, validate high-speed buses"
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top