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Improving PIC32 performance

Posted: 13 Feb 2009     Print Version  Bookmark and Share

Keywords:PIC32  SRAM memory  registers 

According to the book Computer Architecture by Hennesey and Patterson, 30 per cent of a RISC CPU�s cycles are spent moving data.1 If the smaller contexts and more flexible register coverage provided by an OCG compiler, can cut that amount by 1/3 (to 20 per cent), the available number of cycles available for processing will increase by about 15 per cent (from 70 per cent to 80 per cent of cycles). At 80 MHz, this is equivalent to increasing the PIC32�s substantial 125 DMIPS capability to 145 DMIPS. In addition, since fewer instructions are generated to move data, the code size is smaller and the amount of SRAM required for the stack is also smaller, potentially allowing the use of a less expensive microcontroller with smaller flash and SRAM memories.

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Table: Cycles and code vs register and stack usage.

Dynamic context generation
In the case of interrupts, again, a conventional compiler has no way of knowing which registers are used by the interrupt code. In the absence of this information, a conventional compiler must take a conservative approach and save every register that might be used by an interrupt. The amount of context switching code is directly related to the number of registers the compiler saves in response to an interrupt, and this overly conservative approach can result in significantly increased interrupt latency.

In contrast, an OCG compiler knows exactly which registers will be used by every interrupt function in the program. Therefore, it has the intelligence to minimise the size of the context that needs to be switched. This capability improves performance and reduces code size by limiting the number of save and store instructions that must be generated and executed. It also conserves SRAM resources by minimising the amount of SRAM that is used to store saved registers.

Depending on the application, the cycle savings can be substantial. When compiled by a conventional, non-OCG compiler, a simple benchmark program with 65,535 interrupts requires over 8,650,624 cycles for the PIC32 to execute at 80 MHz with 2 wait states. The same program, compiled by an OCG compiler takes only 6,356,898 cycles—or 26.5 per cent fewer cycles. In an interrupt- intensive program, the OCG compiler would give the CPU the equivalent of a near-25 per cent performance boost (Figure 6).

As embedded programs become more sensor-driven and interrupt intensive, minimising interrupt overhead becomes an important component of getting the best performance possible from the PIC32 microcontroller. Part of this responsibility falls on the software engineer, who should take care to keep interrupts as small as possible. In addition, care should be taken to select a compiler with the intelligence to minimise the number of registers to be saved so interrupt latency is lower and CPU cycles are conserved for other computation.

Footnotes: 1 Computer Architecture, John L, Hennesey & David A. Patterson, Morgan Kauffman Publishers, 1990.

- Jeffrey O�Keefe and Matt Luckman
  HI-TECH Software

View the PDF document for more information.


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