Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Interface
 
 
Interface  

Intel lists challenges for chip scaling

Posted: 12 Feb 2009     Print Version  Bookmark and Share

Keywords:chip scaling  interconnect  transistor  lithography 

4. Embedded memory
Problem: High-density memory beyond SRAM is needed in today's devices.

Current solution: Traditional 6T SRAM cells are used in processors and other products.

Future solutions: "In additional to traditional DRAM, eDRAM and flash-memory options, floating body cell, phase-change memory and seek-and-scan probe memory options all provide greater bit density than what 6T SRAM cells can provide. But integrating a novel memory process together with a logic process on a single wafer without compromising one or the other could be difficult."

5. System integration
Problem: It is not sufficient to take smaller transistors as they become available to simply make more complex versions of the same system components.

Current solutions: "The new era of microprocessor scaling makes greater use of energy efficiency, power management, parallelism, adaptive circuits and SoC features to provide products that are many-core, multi-core and multi-function."

Future solutions: "As we ponder the best paths to take in doing higher level integration in the electronics world, we may consider examples provided by nature (such as the human brain).

- Mark LaPedus
EE Times


 First Page Previous Page 1 • 2



Comment on "Intel lists challenges for chip scal..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top