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Tech challenges for 22-nm node

Posted: 06 Jan 2009     Print Version  Bookmark and Share

Keywords:22-nm node  process technology  IC-production 

Leading-edge chip makers are currently in 22-nm R&D. So what are the big challenges ahead at the 22-nm node?

A team of expert analysts from Semiconductor Insights, Xu Chang, Vu Ho, Ramesh Kuchibhatla, and Don Scansen, came up with a list of top challenges for the 22-nm node.

Here's a list of 15 challenges (and more):

1. Cost and affordability

Cost of research and development, process technology, design-for-manufacturing (DFM) and other pieces of the IC-production puzzle continue to soar. Here's the big question: Do product volumes support the economic equation?

2. Scaling

Scaling is nearing the limit. So do we start changing the channel material? So far, a lot of work is done outside the channel, thereby keeping it pristine. Many are looking at germanium for the channel, which has a lot of potential for the required bandgap.

3. Lithography

New technologies like extreme ultraviolet (EUV) and maskless electron-beam lithography will not be ready for production. 193-nm immersion lithography will be extended to 22-nm with the help of double patterning.

4. Transistor architecture

Planar devices will likely be extended to 22-nm. Multi-gate MOSFETs like Intel's tri-gate transistor and IBM's FinFETs have significant challenges with parasitic capacitance, parasitic resistance, among others.

5. Bulk silicon or silicon-on-insulator (SOI)

Bulk vs. SOI? No clear favourite for 22-nm—yet. Maybe both will be used.

6. High-k/metal-gate

Replacement gate integration approach will be challenging due to narrower gate lengths. Zirconium oxide will be required for the scaling down of equivalent oxide thickness (EOT).

7. Strain technology

Various technologies, including stress memorisation techniques (SMT) and tensile stress liner, have been used and embedded Si-C may be needed to improve NMOS current drive. Embedded silicon germanium (SiGe), compressive stress liner and channel/substrate orientation will be needed to boost PMOS performance.

8. Interlayer dielectric

Ultra low-k dielectric or air gap technology will be required as well as new barrier materials for copper. Further reduction of ''K'' value from 2.6 to 2.2 will be necessary to reduce coupling capacitance. Porous carbon-doped oxide materials will be needed.

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