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Embedded design enters a new age

Posted: 19 Dec 2008     Print Version  Bookmark and Share

Keywords:microprocessors  FPGA  IP  licence  licensing 

FPGA designers are embedding soft microprocessors in an increasing number of designs. As a result, FPGA vendors and third-party IP vendors have developed a number of soft microprocessors that are licensed in a variety of ways including the most recent model, open source.

Because designers typically will invest significant time in the development of software code for their soft microprocessors, it is important that they understand the implications of the associated licensing models.

Difficult decisions
Once the decision to implement a soft microprocessor is made, designers must determine which licensing model best meets their needs. There are four principal licensing models used by FPGA vendors for soft microprocessors and MCUs.

Third-party IP vendors most typically use the paid IP model. Although the approaches taken by the third-party vendors are not discussed in this article, most of them are similar to those of the FPGA vendors.

Model 1: Paid IP—The traditional model for supplying soft microprocessors for FPGAs is paid IP. This delivery model presents four challenges:

• A fee must be paid for the right to use the microprocessor development tools and the HDL code that is produced. To continue to use the tools, say for software maintenance, this fee often recurs annually.
• The HDL description of the microprocessor typically is encrypted, limiting the designer's ability to optimise the implementation and leaving the designer dependent on the FPGA vendor for bug fixes.
• Development resources to support the microprocessor are limited to those the FPGA vendor chooses. The vendor, not the designer, defines resource priorities.
• Paid IP licensing terms typically limit implementations to the vendor's FPGA devices. As designers amass code developed for the microprocessor it becomes increasingly difficult to move to another FPGA vendor, a fact known all too well by the vendors.
• The designer's virtual inability to switch vendors eliminates competitive pressure on the vendor, which can lead to less customer attention and limited future price concessions.

Figure: The LatticeMico32 IP core consumes minimal device resources, while maintaining performance required for a broad application set.

Model 2: Free reference designs—The free reference design approach removes two of the challenges associated with the paid IP model. The lack of an upfront fee is certainly attractive, and the fact that these designs are invariably provided in source code format allows for access to the design's structure.

However, ownership of the design by the FPGA vendor eliminates any incentive to develop additional code for the design. Finally, as with paid IP, implementation of the reference design is limited to the vendor's device architecture.

Model 3: Encrypted IP—This is a novel attempt to address some of the challenges of the paid IP approach. In this model, IP is incorporated within a design using the FPGA design tools and the encrypted bitstream that is generated.


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