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Intel to extend lead in high-k

Posted: 12 Dec 2008     Print Version  Bookmark and Share

Keywords:high-k/metal-gate  IEDM  microprocessor 

Moving to 32nm
At IEDM, Intel will present several papers on the subject, including at 32nm. As far back as late-2007, the chip giant rolled out its initial 32nm test chip. The device has a 0.171µ² cell size containing more than 1.9 billion transistors.

Then, in October of 2008, the company tipped its 32nm process. As reported, the process incorporates copper interconnects, a second-generation high-k/metal-gate technology and a fourth-generation strained-silicon scheme.

Intel is expected to deploy its first immersion lithography scanners at 32nm. The 193nm machines will be sole sourced from Nikon Corp.

The transistors feature dual band-edge workfunction metal gates and high-k gate dielectrics with an equivalent oxide thickness (EOT) of 9nm or 9Å. In comparison, the company's 45nm high-k designs have an EOT of 10nm. The 32nm version enables Intel to reduce transistor variability," Bohr said.

At 32nm, Intel's transistor gate pitch is 112.5nm. Intel's 32nm logic technology provides about 70 per cent linear feature size scaling and 50 per cent area scaling, as compared to the company's 45nm process. In addition, the process enables the highest drive currents reported to date for 32nm technology.

Intel is on track for 32nm production readiness in Q4 09. Meanwhile, the company is also working on its 22nm process. The technology will make use of 193nm immersion scanners with either double-patterning or computational lithography techniques, he said. For 22nm, EUV "probably won't be ready," he said.

- Mark LaPedus
EE Times


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