Global Sources
EE Times-India
 
EE Times-India > EDA/IP
 
 
EDA/IP  

Accelerate functional verification

Posted: 25 Nov 2008     Print Version  Bookmark and Share

Keywords:SoC  functional verification 

Rising design complexity, increasingly intricate hardware/software interactions and rising demand for lower power operation are putting pressure on SoC functional verification strategies. These trends present threats to SoC predictability and product development schedules.

A new interactive methodology offers an answer to the escalating challenges. The new approach promises to simplify the adoption and proliferation of new verification technologies and improve communication and reuse across functional groups.

View the PDF document for more information.





Comment on "Accelerate functional verification"
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top