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Manage power in FPGAs using CPLDs

Posted: 25 Nov 2008     Print Version  Bookmark and Share

Keywords:CoolRunner-II CPLDs  Virtex-II  Spartan-3 FPGAs 

All chips draw power, but some applications are more sensitive than others to the amount drawn. Portable applications are sensitive simply because they draw from a battery. Most digital chips are designed to operate at 5V, 3.3V, 2.5V and 1.8V. This does not match well with today's battery voltages. Hence, there will be a regulator or two on most boards. Managing power will involve managing those regulators.

CoolRunner-II CPLDs were designed to operate with a core voltage of 1.8V, well suited to its 0.18µm core, but its I/O structure supports 3.3V, 2.5V, 1.8V and 1.5V operation. Being standard low power CMOS, the I/Os also operate within that range, but are only speed specified at those voltages.

This application note by Xilinx demonstrates how multiple devices, including Virtex-II and Spartan-3 FPGAs, can be effectively power managed by a single CoolRunner-II CPLD. It is written with battery powered applications in mind.

View the PDF document for more information.





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