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Get smart about reset

Posted: 20 Nov 2008     Print Version  Bookmark and Share

Keywords:digital design  global reset  FPGA 

One of the commandments of digital design states, "Thou shalt have a master reset for all flip-flops so that the test engineer will love you, and your simulations will not remain undefined for time eternal."

So, some may be surprised to learn that applying a global reset to your FPGA designs is not a very good idea and should be avoided. Clearly, this is a controversial issue, so this Xilinx application note discusses the reasons why such a design policy should be considered.

View the PDF document for more information.





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