Global Sources
EE Times-India
 
EE Times-India > EDA/IP
 
 
EDA/IP  

New techs address 40nm, 65nm design issues

Posted: 17 Nov 2008     Print Version  Bookmark and Share

Keywords:design issues  custom silicon  ASIC industry  65nm nodes 

Fabless ASIC company Open-Silicon Inc. has announced new technologies that responds to design issues common to the 40nm and 65nm nodes. Based on customer's needs, Open-Silicon said it will use the PowerMAX, CoreMAX and VariMAX technologies to build better custom silicon by designing in lower power, increased performance and managed process variability.

"By combining the ASIC industry's only transistor-level optimisation flow with techniques like back biasing, which are new to the ASIC space, Open-Silicon can build the best possible fully customised silicon in smaller process geometries," said Satya Gupta, VP, engineering and co-founder of Open-Silicon, in a statement.

The company said CoreMAX was created to build the fastest processor cores in the ASIC world. It added that the technology comes out of the Open-Silicon acquisition of Zenasis Technologies in 2007 and uses more than 20 lakh lines of C++ software and several patented techniques to move beyond the limitations of traditional library-based ASIC design.

It noted that built-in CoreMAX functions include design Boolean analysis and optimisation, static timing, cell placement, route estimation and simultaneous optimisation at the logical, physical, and transistor levels.

"VariMAX addresses increasing process variability with a back biasing design approach where the bulk transistor node voltage is controlled so that fast, leaky parts are reined in by adaptive calibration of the silicon," Open-Silicon said.

PowerMAX emphasises low power. Open-Silicon said it has already completed state-of-the-art 65nm designs using power savings methods like low-power place-and-route, voltage islands, power gating, clock gating, and multi-Vt. PowerMAX adds to this foundation with four new technologies: transistor level transformations, back biasing, power recovery, and custom leakage signoff, the company added.

All products are available for design use today, it noted.

- Dylan McGrath
EE Times





Comment on "New techs address 40nm, 65nm design ..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top