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Demystify power gating, stop leakage cold

Posted: 06 Nov 2008     Print Version  Bookmark and Share

Keywords:power gating  nanometer designs  form factor 

Low power or power efficiency is a key design requirement for nanometer designs today. The market for consumer and wireless devices is rapidly changing, driven by the convergence of applications, standards and usage. In order for these devices to deliver additional functionality without compromising on form factor or battery life, they need to employ aggressive leakage power reduction. Logic modules must be shut down when they are not required in operation. Power gating is emerging as the technique to address this complex challenge.

Power gating is the only technique that can address the power challenges of today's nanometer IC designs. This article provides insights into this methodology to demystify any apprehensions about its implementation. An implementation solution that is capable of optimising for gate size, gate control slew rate and simultaneous switching capacitance while minimising leakage must be aware of power domains from synthesis through implementation and verification. Such a solution can help designers successfully achieve design completion using power gating techniques.

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