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Reducing ripple with constant on-time voltage regulator

Posted: 24 Oct 2008     Print Version  Bookmark and Share

Keywords:hysteretic design  switching frequency  output ripple 

One of the biggest disadvantages of the hysteretic design is the very large variation in switching frequency that is observed as the input voltage varies. Here is an attempt to improve this situation with constant on-time control. This article by Craig Varga of National Semiconductor discusses how a constant-on-time based regulator design is capable of delivering low output ripple while still maintaining much of the original simplicity.

An example of a voltage regulator control strategy is the hysteretic regulator. This control methodology simply turns a switch on when the output voltage is below a reference and turns the switch off when the output rises to a slightly higher reference. The output ripple is therefore a direct function of the hysteresis level.

View the PDF document for more information.





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