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Upgraded tool adds SDC support

Posted: 24 Oct 2008     Print Version  Bookmark and Share

Keywords:FPGA  ASIC design  interface timing  SDC 

EMA Design Automation has announced TimingDesigner version 9.1, adding support for SDC which provides the ability to interface with FPGA and ASIC design flows.

TimingDesigner provides an easy to use and intuitive method for defining and analysing interface timing requirements. The introduction of version 9.1 makes TimingDesigner the only tool that can generate SDC timing constraints from a timing diagram. This enables users to visually define design requirements and then automatically generate SDC to drive place and route.

Generating SDC directly from a timing diagram removes any confusion as to the intent behind the constraints and allows users to visually debug and refine their SDC with ease. It also greatly reduces the learning curve for users new to the SDC format.

The initial release of TimingDesigner with SDC support focuses on the Altera FPGA design flow. "Altera works closely with the EMA development team to enable a tight, seamless interface between our Quartus II software and TimingDesigner," said Chris Balough, senior director of software, embedded, and DSP marketing at Altera. "As a result of this effort, customers can leverage the graphical timing analysis features of TimingDesigner to rapidly develop their SDC timing constraints for Altera devices, with the overall system requirements in mind."

TimingDesigner 9.1 will be available at the end of October starting at Rs.1.29 lakh ($2,995) and is free to existing customers with a valid maintenance contract.





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