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Killer app for cellular handsets

Posted: 22 Oct 2008     Print Version  Bookmark and Share

Keywords:Package-on-package  cellular handsets  PoP stacking  chip set 

To continue the Moore's law trend towards smaller handheld devices, designers can leverage advanced packaging and interconnect methods to meet the miniaturisation requirements.

PoP (Package-on-package) stacking technology has found its killer app in the cellular handset. Smart-phone handsets require both state-of-the-art semiconductors and packaging technology to meet changing size and functionality demands while meeting strict manufacturing cost and reliability requirements.

The advantages of PoP stacking extend beyond area savings. Many handset designs can be created with a basic platform approach—similar to that of a PC -by combining the PCB, chip set and various peripheral components to make phones with specific feature sets. Chip sets in these devices are often designed to accommodate package stacking, which helps make derivative products from a base design. One common method varies the amount of memory to differentiate one product from another.

When the memory is placed in PoP stacks, it's simple to substitute one or more memory components in the stack. Each stack contains a different amount of memory or set of features. In this way, a family of products can be quickly and easily implemented; changing the number and density of memory components differentiates the product offerings in a family. Apple, for instance, introduced the iPhone in 4GB and 8GB configurations as an assembly-time build-option. This gives Apple the flexibility to build a 4GB or 8GB configuration by selecting the appropriate stack of memory; the configuration can be the last decision before assembly. The approach permits quick reactions to changing component supply or handset demand.

Die stacking alone requires stacking variants be made when die are assembled into packages rather than during final assembly of the end product. PoP stacking streamlines the process, permitting end-product manufacturers to stack different component sets together and allowing changes late in the process. This speeds deployment of derivative products, works as an alternate supply model and allows assembly subcontractors to supply completed stack subassemblies ready for final assembly.

3D stacks also simplify PCB designs by decreasing wire routing and saving layers. In PCB assembly, the stacks reduce the number of piece parts to be picked and placed, improving assembly throughput and yield.

The supporting infrastructure of component vendors, assembly equipment suppliers and package vendors working to develop standards make the advantages of PoP stacking possible. By the end of 2007, 15 major logic IDMs, eight major memory suppliers, six assembly equipment vendors and five EMS/CM assembly houses all agreed to support PoP stacking. In addition to base band processors stacked with memory, application processors, image processors, FPGAs and other system logic chips are being developed for stacked packaging.

In PoP stacking, components are stacked after die packaging. Depending on the package, POP stacks may be significantly thicker and have greater mass than stacks of bare die. To resolve this, some companies are developing thinner stackable packages.

Tessera's MicroPILR platform, based on an etched copper pin technology, offers significantly reduced lead pitch over conventional BGA technology. It allows nickel/gold-plated copper pins to be placed as closely as a 150µm; pitch to support advanced PoP stacking requirements, including large area arrays or tall stacks of memory.

-Richard Crisp
EE Times





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