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Implementing S29WS256N using 3.3V system bus

Posted: 10 Oct 2008     Print Version  Bookmark and Share

Keywords:S29WS256N implementation  3.3V system bus 

This application note describes the implementation of the S29WS256N using a 3.3V system bus.

In order to use the S29WS256N on a 3.3V system, that is, FPGAs, ASICs, MPUs, MCUs and other digital devices, voltage translation buffers are needed on the address, data and control lines. For example, if a board uses a 1.8V Spansion flash and a 3.3V CPU, the board can encounter problems since the typical minimum legal low for 3.3V CPU is higher than the source voltage of the 1.8V flash. Also, the minimum legal high level output signal is an invalid level for a 3.3V CPU.

View the PDF document for more information.





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