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Building Xtensa-based emulation system on Xilinx FPGA

Posted: 29 Sep 2008     Print Version  Bookmark and Share

Keywords:FPGA  SoC design  Xilinx logic 

This application note explains how to map an Xtensa or Diamond core to an FPGA with a minimal on-chip system. This application note includes a demonstration example of an FPGA flow based upon Xilinx logic using RTL for the 108Mini Diamond core.

During system development there is a need for a SoC design to be available to perform software development, demonstration, and verification of the design. Use of an FPGA-based emulation system can be used early in the development cycle, before the silicon-based SoC is available. FPGA-based systems are used by programming the FPGA chip with a 'bit stream'. This bit stream represents the design and affects the chip to cause it to function as the SoC design (emulation).

Often an FPGA board contains PROMs that can be used at power on to program the FPGA chip so that the user needn't program it each time the FPGA board is powered on. Along with this application note there are several files including a 'make' flow that supports two modes to build bit streams or PROM files. The default process of this make flow will build Xilinx FPGA-ready bit stream and PROM files. The default flow is intended to build a 'sample system'. The second (user) mode of the flow provided allows for you to override many of the defaults to adapt this flow to your SoC FPGA needs.

View the PDF document for more information.





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