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Start-up Achronix samples 1.5GHz FPGA

Posted: 18 Sep 2008     Print Version  Bookmark and Share

Keywords:asynchronous circuitry  1.5GHz FPGA  ASIC  65nm device 

Achronix Semiconductor Corp. is using asynchronous circuitry to deliver a 1.5GHz FPGA now sampling. The start-up hopes to use its three-fold lead in data rates to grab ASICs sockets in high-end communications, test and other systems beyond the reach of existing parts from Altera, Xilinx and others.

Whether Achronix can deliver on the promise of its technology remains to be seen. It is lining up a suite of tools and silicon intellectual property for its part which it says will be in production in 1H 09.

The new 65nm device represents a second attempt at a commercial product. About a year ago, the company killed its so-called Ultra chip—a 90nm, 1.93GHz version announced in 2006, saying it lacked the mix of features users wanted.

"Assuming they can deliver, they would be filling a void that's existed for quite awhile, providing a new top end for the FPGA market," said Rich Wawrzyniak, an analyst with Semico Research. "There's always been a pretty wide gap between the top end of ASICs and FPGAs."

"It's certainly a viable approach to take," said David Greenfield, senior director of product marketing for high-end FPGAs at Altera, speaking of a move to faster data rates. "We have looked at it before and will continue to look at it," he said.

Altera decided to build more dense products rather than faster ones with its 40nm chips set to ship later this year. The new Stratix parts will have the same native speeds of about 350MHz of its existing 65nm chips, but the new chips will double to as many as 700,000 the number of logic elements. They will support hard cores running at up to 550 MHz.

"There are multiple ways to address performance in the critical path for any particular design, sometimes it's through the clock and sometimes its elsewhere," said Greenfield. Only about ten per cent of customers for Altera's Hard Copy FPGA-to-ASIC service are seeking its 30-50 per cent higher data rates, he added.

The Achronix SPD60 is built up from relatively conventional four-input look up tables (LUTs) encapsulated in a 1.5GHz synchronous logic. Inside that frame the chip employs routing elements made up from basic transmit and receive components that use asynchronous acknowledgements rather than clock cycles to stage the flow of data.

The approach allows higher throughput than traditional flip-flops that gate logic elements in traditional FPGAs. It emerged from research in asynchronous logic by two company founders—Rajit Manohar, an associate professor at the School of Electrical and Computer Engineering at Cornell University and one of his doctoral students, Clint Kelly.

The start-up envisions a family of four Speedster chips all running at up to 1.5GHz and supporting up to four 1,066MHz DDR3 memory controllers. The initial SPD60 includes 47,000 look-up tables and can hold up to 20 10.3Gbit Serdes licensed from the former Snowbush Microelectronics.

Achronix plans to follow up the part with a high end SPD180 with 163,000 LUTs and room for twice as many 10G Serdes. A low end part will have two memory controllers, 24,000 LUTs and fit in a 31mm x 31mm package. The devices will range widely in price and power consumption from Rs.8,571.69 ($200) and less than 20W to Rs.1.07 lakh ($2,500) and more than 40W.

Holt claims the family can address a Rs.7,285.94 crore ($1.7 billion) slice of the ASIC market that traditional FPGAs cannot reach. "We can become a billion-dollar company without winning a single existing Xilinx or Altera socket," Holt said.

Achronix had announced in 2006 its 1.93GHz Ultra chip built in a 90nm process at Chartered Semiconductor. But the start-up soon found it lacked features prospective users demanded and consumed more power than they would tolerate.

The Ultra had about half the density of the currently sampling product and significantly higher power consumption. It also lacked support for 10G serdes which was only available at the time in a block from Snowbush designed for a 65nm TSMC process.

"Not having a 10G serdes could have excluded us from communications systems—a third of our potential market," said Holt. The 65nm TSMC process also could accommodate a broader product family, he added.

Engineers are hammering out standards for 40Gbps and 100Gbps Ethernet systems that carriers are eager to deploy in their core networks. While that work is not yet complete, many believe 10G serdes will be key to supporting the specs.

"We think demand for [10G serdes] will kick in early next year," said Greenfield of Altera. "Verizon, AT&T and others want to deploy these 40Gbit and 100Gbit systems as early as 2010, so they need to do field trials in late 2009 and that means having chips in the lab in early 2009," he added.

Altera already has running in its labs internally designed 10G serdes that will be available for its FPGAs early next year, Greenfield said. Its 40nm FPGAs will initially ship late this year with its 8.5G serdes.

Many new chip architectures sport breakthrough performance at the cost of requiring radically new programming tools. Early on, Holt insisted the Achronix parts should resemble traditional FPGAs so they could use existing tools as much as possible.

Thanks to its synchronous frame and use of traditionally organised LUTs, Achronix was able to get support in versions of front-end tools including Mentor Graphics' Precision and Synplify Pro from Synopsys (formerly Synplicity).

"A lot of other FPGA start-ups would not even be able to get support from a Mentor or Synplicity," said Holt. "Some of these guys even require schematic entry or by-hand design."

In January, Achronix shipped its own back-end tool that handles place and route, timing and critical path analysis. It aims to support a look-and-feel roughly similar to tools from Altera and Xilinx.

At the board level, "other chips don't have to know anything about our oddball architecture," said W. Denny Scharf, strategic marketing manager for Achronix. "People can implement a design without even realising this is asynchronous," he said.

As for silicon IP, the start-up claims it has a long list of partners whose blocks can be readily implemented on the chip. They include a broad range of interfaces blocks including Gbit and 10Gbit Ethernet, 2.5GHz and 5GHz PCIe, Infiniband and Fibre Channel. The company has also licensed a 32bit processor core from Cortus S.A.

Achronix took in Rs.147.43 crore ($34.4 million) in venture funding in a Series A round in 2007. Prior to that time it was self-funded.

- Rick Merritt
EE Times





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