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IBM rolls 'computational scaling' for 22-nm node

Posted: 19 Sep 2008     Print Version  Bookmark and Share

Keywords:22-nm node  ''computational scaling''  193-nm immersion  source-mask optimisation 

Amid probable delays with extreme ultraviolet (EUV) lithography, IBM Corp. plans to extend 193-nm immersion and move towards what the company calls ''computational scaling'' technology for the 22-nm node and perhaps beyond.

IBM also announced its new ecosystem partners for the technology, including EDA house Mentor Graphics Corp. and photomask maker Toppan Printing Ltd.

Current optical lithography is expected to hit the wall at the 32-nm node. ''Computational scaling''—sometimes called computational lithography—is said to overcome those limits and extend 193-nm immersion.

A key to ''computation scaling'' is a partnership between IBM and Mentor, which plans to devise a new resolution enhancement technique (RET) to enable 22-nm designs and perhaps beyond. This RET technology, know as source-mask optimisation, will not eliminate dreaded and expensive 193-nm immersion—with double-patterning techniques.

Source-mask optimisation is said to optimise both mask layout and illumination simultaneously to maximise image contrast in a scanner. The technology is said to provide a means to minimise the use of double-patterning by employing customised sources within the scanner, along with optimised mask shapes.

There are other components to ''computational scaling:'' virtual silicon processing with TCAD; predictive process modelling; design-rule generation and corresponding models; design tooling; design enablement; complex illumination; variance control; and mask fabrication.

For some time, computation lithography, source-mask optimisation and related technologies have been discussed and debated at technical events. It remains to be seen if some or all of these technologies can be put in production fabs, but chip makers may have little or no choice.

At 45-nm, IBM and other leading-edge chip makers are processing chips with 193-nm immersion lithography. In contrast, Intel Corp. is currently using 193-nm ''dry'' lithography at 45-nm.

All leading-edge chip makers will deploy 193-nm immersion lithography with some form of double-patterning technology. In double-patterning, the wafer is exposed twice, thereby increasing overall chip production costs.

Beyond 32-nm, there are no viable lithography solutions right now. The industry has put its weight behind EUV, but the technology is late to the party due to the lack of power sources, resists and masks.

EUV is now targeted by some for 22-nm, but others doubt the technology will be ready in time for that node. '' I don't see that happening,'' Subramanian Iyer, chief technologist for the Semiconductor Research and Development Centre within IBM's Systems and Technology Group.

EUV is making progress, but the technology ''is not mature,'' he told EE Times at a press event here. The new target for EUV is the 16-nm node, he added.

Enter ''computation scaling.'' In some ways, IBM and Mentor have been working on the technology for some time.

Earlier this year, IBM qualified Mentor Graphics' Calibre nmOPC and OPCverify computational lithography tools, which are accelerated with IBM's Cell processor technology, for production at 45-nm and smaller process nodes.

Performance requirements for computational chip lithography are outrunning the performance of general-purpose computing platforms. To address the problem, Mentor Graphics recently partnered with Mercury Computer Systems to optimise Calibre nmOPC and OPCverify software for the Cell Broadband Enginer processor.

Mercury provided a pre-integrated coprocessor acceleration (CPA) cluster including Cell BE blades as part of an IBM BladeCentre H system. Connecting the CPA cluster to users' existing standard computer clusters was said to provide big reductions in turnaround time and cost for advanced lithography.

Activity in the computational lithography area is heating up. At the recent SPIE conference, Brion introduced its Tachyon 2.5, an optical proximity correction verification accelerator aimed at 32- and 22-nm designs. It also unveiled its Tachyon DPT aimed at the double-patterning lithography in advanced chip designs.

- Mark LaPedus
EE Times





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