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EDA/IP  

Verification IP reuse for complex networking ASICs

Posted: 18 Sep 2008     Print Version  Bookmark and Share

Keywords:ASIC  verification  IP reuse 

This paper presents a verification environment that lays down the methodology blueprint for future ASIC verification projects and stretches the boundary of IP reuse by finding sources and consumers of verification IPs in other aspects of the product development cycle including modelling, multi-chip co-simulation, and software debugging.

With the goal of maximising verification IP reuse, this verification environment can shorten a project cycle of a brand new three million-gate design to seven months, compared to the typical nine-month cycle.

View the PDF document for more information.





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