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C-based coprocessor design: SIMD architecture

Posted: 18 Sep 2008     Print Version  Bookmark and Share

Keywords:ESL  SIMD  coprocessor  synthesis tools 

With the introduction of disruptive electronic system level (ESL) synthesis tools, large-scale accelerators can be described at a higher abstraction level. At the same time, the processor architect maintains full control over the ESL synthesis process by using precise interface inference, user-specified clocking, explicit data level (DLP) and thread level parallelism (TLP), as well as combinatorial logic.

This article elaborates on the use of ESL for implementing a 2-way LIW/SIMD hybrid accelerator, attached to a scalar processor core, with configurable micro-architecture and programmer's model/ISA. The novelty of this work relies in the fusion of the configurable processor and ESL implementation domains in a unique way by using ESL as the implementation medium not only of custom SIMD extensions, but of a whole parallel coprocessor.

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