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Sematech shows progress on EUV at 22 nm

Posted: 14 Aug 2008     Print Version  Bookmark and Share

Keywords:extreme ultraviolet  EUV lithography  silicon devices  semiconductor node 

Sematech has demonstrated a way of using extreme ultraviolet (EUV) lithography to define silicon devices with a half-pitch resolution as small as 22 nm. The company says that is also close to being able to define features smaller than 20 nm. The chip research consortium says the work shows the promise of EUV to serve a future 22 nm semiconductor node.

Engineers have been racing to develop ways to create devices for a 22 nm semiconductor technology, just two generations beyond the 45 nm process leading chip makers such as Intel Corp. are using for their microprocessors today. As recently as last month's Semicon West conference, speculation was rising that EUV would not be ready for the 22 nm node, fueling work on extending a double-patterning lithography being developed for the 32 nm node.

Sematech announced Tuesday (Aug. 12) it has worked with major resist suppliers to demonstrate a chemically-amplified EUV resist platform that supports 22 nm half-pitch resolution. The group said it is "close to resolving" sub-20nm half-pitch features.

"Enabling 22 nm half-pitch resist goes a long way towards enabling the technology as a whole," said Stefan Wurm, program manager for EUV at Sematech in an email exchange.

"These results mark a cornerstone in the development of EUV lithography," said John Warlaumont, vice president of advanced technology at Sematech, in a prepared statement. "They represent the first real 22 nm resist data, building confidence for EUV as a viable technology for 22nm half-pitch lithography," he added.

Trade-off
The Sematech results showed an acceptable photospeed (at 15 mJ/ cm2), but line width roughness at 5- to 6nm was higher than specified in the International Technology Roadmap for Semiconductors (ITRS), the industry's chip road map. Sematech expects that resist post processing and etch processes are likely to bring down roughness down to a value that is acceptable for early adopters in DRAM and flash memory chips.

The trade-off between resist resolution, line width roughness and photospeed is one of the key challenges that need to be overcome to enable EUVL, said Wurm.

"This achievement [of a 22 nm demo] was deemed to be impossible by leading resist experts only a few years ago," said Chawon Koh, an EUV resist process engineer leading the joint evaluation of resist platforms between Sematech and resist suppliers.

Koh attributed the advance in part to the use of micro-exposure tools at located at the University at Albany's College of Nanoscale Science and Engineering and at University of California at Berkeley. The new tools helped researchers at Sematech's EUV Resist Test Centre in Albany, demonstrate a 35nm half-pitch resolution barrier in 2006 and a 26- to 28nm half-pitch devices more recently.

The EUV resist work is just one piece of the puzzle—albeit an important one—needed to deliver a fully 22 nm process node. Due to delays in delivering all the parts of the complex technology, some developers have raised concerns EUV lithography may not be fully ready for commercial use until a 16 nm node, forcing engineers to extend methods currently planned for the 32nm process.

The ITRS road map targets volume manufacturing of 22 nm half pitch technology by 2016, although some chip makers are likely to start using the technology sooner. To take resists from the development phase to manufacturing "takes a long time" especially if new resist platforms are required, Wurm said in the email exchange.

Outside EUV, Sematech has programmes in extensions to existing 193nm immersion lithography. The group is also evaluating or monitoring alternative technologies such as nanoimprint and maskless lithography, he said.

"The focus of Sematech's EUV resist development programme is to engineer platforms to realise 22 nm high pitch introduction and provide a fundamental understanding of EUV resist exposure mechanisms to develop new platforms," said Wurm in the Sematech press statement. "We believe this two-pronged approach will drive resist development to the highest level and support EUV introduction."

- Rick Merritt
EE Times





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