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DDR2 PCB design: get it right the first time

Posted: 04 Aug 2008     Print Version  Bookmark and Share

Keywords:PBC layout  DDR2  DRAM 

DDR2 is the next memory standard. To design a successful DDR2 interface to SDRAMs, the skew between data and strobe, power supply jitter, crosstalk, reflections, attenuation and other considerations must be balanced. If certain design rules are not followed, the consequences may affect the interface's functionality. This article explains how a DDR2 system works and describes from a designer's point of view the correct way to implement it on a PCB.

DDR2 is similar to DDR in that it is a source synchronous interface; the clock is sourced by the same device that generates data signals. It uses the same process to read and write data on the clock signal's (CK) rising and falling edges. However, DDR2 can process 4bits of information per clock cycle, compared with DDR's 2bits. DDR2 also offers more efficient memory architecture in the areas of data transfer power-saving: on-die termination (ODT), additive latency and power consumption.

ODT is built into the DDR2 chip module. A termination resistor is placed on the module to eliminate the need for any termination on the motherboard. This helps move data signals to and from the DRAM without injecting excessive noise. What's more, a DDR2 memory interface provides additional latency by delaying a read command internally before being executed. This lessens the occurrence of data collisions and provides a more reliable memory interface. At the same time, DDR2 operates at 1.8V compared with DDR's 2.5V and thus runs cooler.

A typical DDR2 interface comprises a memory interface controller (MIC), DRAMs and a buffer chip that redistributes clock and address to the DRAMs. The DDR2 memory bus is comprised of signals divided into data, address and command, control and clock groups.

The data group is composed of bidirectional data bits (DQ). Each DQ group shares the same strobe signal (DQS) and a data mask bit (DM). This group is referred to as a byte lane. During a write operation, DQS is sourced by the MIC. During the read operation, DRAM sources DQS. Data is sampled on both the rising and falling edges.

Address and command signals are unidirectional and always sourced by the MIC. They run at half the frequency of the I/O bus when using 2T clocking, a two-cycle command delay before the MIC can start sending signals to the memory bank, or the same frequency as that of the I/O bus when using 1T.

The control group includes chip select (CS), clock enable (CKE) and ODT signals. This group runs at 1T clocking. ODT signals are used to enable or disable ODT. CKs are usually sourced by the MIC and sample the data (address and control) only on the rising edge.

Layout guidelines

A DDR2 sub-system requires clean reference signals, reduced setup and hold times and length matching to reduce signal skew effects. The recommended routing sequence of the different DDR groups is data, address/command, control and clock.

It is highly preferable to route the data group first as it constitutes the largest portion of the memory bus. Moreover, it operates at twice the clock speed of other groups, and its signal integrity is of most concern.

Data is captured by the MIC (using the DQS rather than the clock) on both rising and falling edges of the strobe. Each 8bit datum (DQ0 to DQ7) has an associated strobe and mask. It is crucial that this "byte lane" be matched in length with the lowest tolerance achievable. Ideally, all byte lanes should be of the same length to each other. It is also important that the board designer provide these signals with a solid reference plane to control the characteristic impedance and have a smaller loop area between the signals and the return currents. Preferably, no vias should be used on these signals, avoiding additional capacitive loading.

Crosstalk is another major concern in a DDR2 layout, where signals of different frequencies are routed near each other. The data group must be kept away from all other groups by at least five times the trace width. It is also important to keep three times clearance between traces within each byte lane.

Conductor and dielectric losses are one of the top contributors to jitter in the DDR2 interface. Conductor losses are caused by the "skin effect" or the tendency of electrons to flow on the surface of the conductors, at higher frequencies. Skin effect can be reduced by increasing the trace widths of the conductors, but the trace width nevertheless must be maintained to a certain value to control impedance.

Dielectric losses result from molecular vibrations of the dielectric near the conductors carrying electrons. These cause some of the energy of the electrons to be absorbed by the dielectric, producing attenuation. These losses can be reduced by using advanced materials with lower loss tangents or dissipation factor.

On a DDR2 memory bus, the address/command group is sourced by MIC and captured at DRAM using memory clocks. Usually, termination resistors are used for these signals and placed behind the last DIMM slot. Their value depends on bus topology.

From a layout perspective, it is important to provide a power/ground reference to these signals to get a solid return path. It is also important to keep these signals away from the data group. Because the address/command group is captured by the memory clock, they must also maintain a length relationship with the CKs, depending on the application.

Most notable of the control signals are the ODTs, which enable and disable the ODT on the data group. DDR2 does not require the use of serial or parallel termination on the data lines unlike DDR. Rather, DDR2 has termination built in by using ODT. Like the address/command group, these signals require a termination resistor placed after the last DIMM slot.

Other similarities to the address/command group include the need for a solid reference plane, clearance requirements with the data lines and maintenance of a length relationship with the memory clock. One thing different about the control group is that it is routed point to point, unlike other signal groups that are daisy-chained.

Meanwhile, DDR2 features differential clock inputs (CK and CK#) to diminish variations in the duty cycle of the clocks. Because the clocks are used to capture command and address data, they must maintain the length relationship to the address/command group. Moreover, during a write cycle, the MIC must satisfy the timing specs between DQS and CK to facilitate the reliable transfer of data. As a result, two main concerns exist when connecting the clocks from the MIC to the DIMM: clock timing and differential impedance.

Board designers should ensure that clock lines are routed differentially and correct trace widths or clearances maintained to achieve the target differential impedance. Routing the signals differentially reduces the flight time of the clocks when compared to the single-ended signals. Because of this, most DDR2 design guides recommend that clock signals be routed at the same length or longer than the address, control and command signals to compensate for this timing variation.

Power play

A DDR2 power system requires VDD, VREF and VTT.

VDD is the main 1.8V supply for the MIC and DRAM. Board designers, much like other designers of high-speed technology, should provide a low impedance power system on the board while meeting every device's switching needs.

VREF is used as a reference voltage by the differential receivers in the DRAM and the MIC. This is done to discriminate between the logic high and low levels at the receiver input. The value is half of VDD (0.9 V).

VTT is the termination supply of the bus that is required at the midpoint voltage. Its value must be within an 80mV range of VREF.

DDR2 will be around for a while. It behoves layout designers to completely comprehend the interface before doing layout so that the boards they design will be "right the first time."

- Syed Wasif Ali
Advanced Certified Designer and Layout Engineer
Nexlogic Technologies Inc.

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