Global Sources
EE Times-India
 
EE Times-India > EDA/IP
 
 
EDA/IP  

Building reliable FPGA memory interface controllers

Posted: 19 Apr 2006     Print Version  Bookmark and Share

Keywords:FPGA  GUI  RTL code  memory interface 

What if a designer could simply use a GUI to input the memory system parameters and generate RTL code without writing it from scratch? What if the physical layer interface was based on hardware verified designs?

Equipped with the right FPGA and software tools, memory interface controller design can be a reasonably pain-free process, even when attempting to access the added performance benefits of today's DDR2 SDRAM with the latest 667Mbps speed grade.

View the PDF document for more information.





Comment on "Building reliable FPGA memory interf..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top