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EDA/IP  

Multi-threaded design tackles SoC performance bottlenecks (2)

Posted: 27 Dec 2006     Print Version  Bookmark and Share

Keywords:multi-threading processor  SoC  bus  processor efficiency 

Coupling processor operation closely to bus and other computational demands leads to a dramatic increase in automotive vision system processor efficiency. With further tuning, optimising the bus to work closely with the hardware threads improves performance and provides a more controllable, measurable, and predictable system latency.

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