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High-speed boards meet PCIe challenge

Posted: 16 Jul 2008     Print Version  Bookmark and Share

Keywords:PCIe  PCI Express  PCB layout  transmitter 

Since its definition in the early 1990's, PCI has emerged as one of the most successful interconnect technologies ever used in computers. Originally intended for PCs, the PCI architecture has penetrated into virtually every computing platform category, including servers, storage, communications and a wide range of embedded control applications. From its early incarnation as a 32bit 33MHz interconnect, it has been expanded to offer increasing speed and bandwidth.

As successful as the PCI architecture has become, there is a limit to what can be accomplished with a multi-drop, parallel shared bus interconnect technology. Issues such as clock skew, high pin count, trace routing restrictions in PCBs, bandwidth and latency requirements, physical scalability and the need to support QoS within a system for a wide variety of applications lead to the definition of the PCI Express (PCIe) architecture.

PCIe is the natural successor to PCI, and was developed to provide the advantages of a state-of-the-art, high-speed serial interconnect technology and packet-based layered architecture, but maintain backward compatibility with the large PCI software infrastructure. The key goal was to provide an optimised and universal interconnect solution for a great variety of future platforms, including desktop, server, workstation, storage, communications and embedded systems.

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